Cache Memory Write Period Controller for MRAM Reliability
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Solution Overview
Problem
Cache memories, particularly MRAMs, face issues with write errors, read disturb, magnetization inversion, and retention failure due to unstable inversion threshold values and characteristic variations in magnetic tunnel junction elements, leading to increased leakage current and latency.
Innovation Solution
A cache memory system with a write period controller that adjusts the write pulse width based on read error frequency and processor performance degradation, using a timing generator to control the write pulse signal and error correction mechanisms to enhance data reliability and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write pulse width is extended to improve data writing reliability, then write error rate decreases, but access latency increases
Solution Approach 1:
The write pulse width is made dynamically adjustable rather than fixed. The controller varies the pulse width based on detected write errors and stability conditions, extending it when reliability is compromised and reducing it when stability is sufficient, thus resolving the contradiction between reliability and latency
Solution Approach 2:
A feedback mechanism monitors write error rates and data stability conditions to automatically adjust the write pulse width. When errors are detected or stability deteriorates, the system increases the pulse width; when conditions improve, it reduces the pulse width, balancing reliability and performance
2Speed
If the read current is increased to improve read speed, then read performance improves, but read disturb errors increase
Solution Approach 1:
The system changes the current parameter dynamically by adjusting the read current magnitude based on detected read disturb errors. When errors are detected, the system reduces the read current to minimize further disturb, while maintaining sufficient read speed through optimized pulse width control
3Reliability
If the inversion threshold value is increased to prevent magnetization inversion, then data retention improves, but write current requirements increase
Solution Approach 1:
The system performs preliminary stabilization of the inversion threshold through controlled write operations and pulse width adjustment before actual data writing occurs. This preliminary action ensures the threshold is stable and appropriate, preventing magnetization inversion during subsequent write operations without requiring excessive current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces error occurrence and correction frequency, improves processor latency, and minimizes power consumption by dynamically adjusting the write pulse width, thereby stabilizing data storage and retrieval processes.
Implementation Method 1
MRAMs (Magnetoresistive RAMS) attract attention as a candidate for a large-capacity cache memory are non-volatile. MRAMs have a feature of much smaller leakage current than SRAMs currently used in the cache memories.
Implementation Method 2
Spin injection magnetization inversion is one of MRAM data writing techniques. In the spin injection magnetization inversion, a write current having a specific current value or larger flows into a magnetic tunnel junction element (MTJ element) of an MRAM.
Implementation Method 3
Also in data reading, a specific read current flows into the MTJ element.
Data Source
AI summary
A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.