Cache Metadata for Deterministic Multi-Core Simulation

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Solution Overview

Problem

Debugging parallel applications in multi-core environments is challenging due to the lack of determinism and repeatability in memory system interleaving, making it difficult to trigger and reproduce bugs, and achieving speedup in high-performance simulation and emulation is hindered by non-deterministic hardware.

Innovation Solution

Implementing a system with metadata in the cache memory that performs load and store checks to detect mismatches, invoking runtime software routines to order memory references and synchronize core permissions, allowing for deterministic execution and simulation with minimal overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel processing is used to achieve faster execution, then productivity is improved, but determinism and repeatability of execution deteriorate

Engineering Contradiction:
Improveexecution speedVSAvoiddeterminism
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by inserting metadata into cache memory before parallel execution begins. This metadata encodes the original sequential order of memory operations, allowing the system to restore determinism after parallel processing by referencing this pre-established ordering information.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses metadata as an intermediary element that mediates between parallel execution and deterministic ordering. The metadata acts as a bridge, carrying ordering information through the parallel processing operations and enabling the system to maintain both parallelism and determinism simultaneously.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If hardware checks are added to ensure determinism, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImprovedeterminismVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by making the cache memory itself store and manage the metadata required for deterministic execution. The cache memory serves its own additional function of tracking operation order without requiring separate external monitoring hardware, thereby reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

3Reliability

If metadata is inserted into cache memory to track memory operations, then determinism is improved, but use of energy increases

Engineering Contradiction:
ImprovedeterminismVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies multi-functionality by making the existing cache memory structure serve dual purposes: storing data for processing and simultaneously storing metadata for deterministic tracking. This eliminates the need for separate dedicated hardware structures, thereby avoiding additional energy consumption that would result from duplicate systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9606924B2System and method for supporting fast and deterministic execution and simulation in multi-core environments
Publication Date: 2017.03.28 WIND RIVER SYSTEMS INC
  • US9606924B2 patent drawing
  • US9606924B2 patent drawing
  • US9606924B2 patent drawing

AI summary

The exemplary embodiments described herein relate to supporting fast and deterministic execution and simulation in multi-core environments. Specifically, the exemplary embodiments relate to systems and methods for implementing determinism in a memory system of a multithreaded computer. A exemplary system comprises a plurality of processors within a multi-processor environment, a cache memory within the processor and including metadata, and a hardware check unit performing one of a load check and a store check on the metadata to detect a respective one of a load metadata mismatch and a store metadata mismatch, and invoking a runtime software routine to order memory references upon a detection of one of the load metadata mismatch and the store metadata mismatch.