Cache Array Micro-Masking for Defect Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional cache memory solutions, such as array masking, significantly impact system performance and cache capacity due to the inability to effectively hide subarray failures in denser cache memory arrays, where masking no longer segregates failures effectively and results in increased cache loss with larger cache sizes.
Innovation Solution
The implementation of a 'compartment bit' and additional address bits for micro-masking allows for selective subarray grouping, enabling system-level masking to hide subarray failures and reduce cache offline, while also enabling power savings during data access by selecting subarray groupings during reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional array masking is used to circumvent defects in cache memory, then defective portions can be masked, but system performance significantly degrades due to loss of overall cache capacity
Solution Approach 1:
The patent segments the cache memory into multiple subarrays within each macro, allowing selective masking of only the defective subarray rather than the entire macro. This is achieved by dividing the cache into compartments using compartment bits and further dividing into subarrays using address bits, enabling granular defect isolation that preserves functional cache capacity and maintains system performance.
Solution Approach 2:
The patent applies local quality by enabling different masking states for different portions of the cache memory. Specifically, it allows selective disabling of write operations for only the defective subarray while leaving other subarrays operational. This localized approach ensures that only the minimum necessary cache portion is masked, preserving overall cache capacity and performance while still achieving defect circumvention.
2Reliability
If conventional array masking is used to mask uncorrectable errors, then defective cache portions can be identified and marked, but cache capacity is significantly reduced
Solution Approach 1:
The patent segments cache memory into hierarchical levels: cache banks divided into macros, macros divided into subarrays, and subarrays into compartments. This multi-level segmentation allows precise identification and masking of only the smallest defective unit (subarray or compartment) rather than larger structures, maximizing the retention of usable cache capacity while maintaining reliable error handling.
Solution Approach 2:
The patent introduces new dimensions for cache organization by adding compartment bits and subarray selection mechanisms to the traditional cache address structure. This dimensional expansion enables fine-grained addressing and masking capabilities, allowing the system to mask only the specific defective subarray while preserving access to all other cache regions, thereby maintaining maximum cache capacity.
3Reliability
If mask bits are enabled for cache portions with uncorrectable errors, then those portions can be excluded from use, but the mask may not cover common EDRAM macro fail mechanisms
Solution Approach 1:
The patent segments the EDRAM macro into multiple subarrays and further into compartments, creating a hierarchical masking structure. This segmentation allows the masking mechanism to cover various fail mechanisms at different granularities - from entire subarrays to specific compartments - providing comprehensive error coverage while maintaining a systematic and manageable masking approach rather than requiring complex ad-hoc solutions for each failure mode.
Solution Approach 2:
The patent implements dynamic masking capabilities where the masking state can be selectively applied to different subarrays and compartments based on detected defects. The system can dynamically adjust which portions are masked versus active, allowing flexible adaptation to different failure scenarios and enabling comprehensive coverage of various EDRAM macro fail mechanisms while keeping the masking logic systematic and extensible.
Data Source
AI summary
A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.