Cache Miss Buffer Segmentation for Parallel Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In cache systems, when a cache miss occurs, the cache line must be fetched from a lower memory level, leading to increased circuit size and power consumption due to the need for a larger data miss buffer to handle multiple simultaneous misses, which slows down subsequent memory access requests.
Innovation Solution
Implementing a data processing apparatus with a limited number of storage elements that replace existing data beats with incoming data beats from different cache lines, allowing for simultaneous handling of multiple misses without waiting for a complete cache line, thereby reducing storage requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of simultaneous cache misses handled is increased, then memory access parallelism is improved, but storage requirements and circuit size increase
Solution Approach 1:
The cache line is segmented into multiple data beats that can be received and stored separately. The data miss buffer is divided into multiple storage elements, each capable of holding a portion of a cache line. This segmentation allows the system to handle multiple cache misses simultaneously by storing data beats from different cache lines in different storage elements, thereby improving memory access parallelism without requiring a single large buffer.
Solution Approach 2:
The storage elements in the data miss buffer are designed to be multi-functional, where each storage element can hold data beats from any cache line rather than being dedicated to a specific cache line. This universality allows the same storage resources to serve multiple cache miss handling operations simultaneously, improving productivity while keeping the circuit size manageable.
2Productivity
If the number of simultaneous cache misses handled is increased, then memory access parallelism is improved, but power consumption increases
Solution Approach 1:
By segmenting the buffer into multiple smaller storage elements, the system can activate only the necessary storage elements for current operations. This reduces the overall power consumption compared to a single large buffer that would need to be fully activated to handle multiple simultaneous misses.
Solution Approach 2:
The data miss buffer implements dynamic allocation of storage elements to active cache miss operations. Storage elements can be dynamically assigned to different cache lines as misses occur and are resolved, allowing the system to scale power consumption with actual usage rather than maintaining full power for maximum capacity.
3Reliability
If data is waited to be complete before processing, then data integrity is ensured, but memory access latency increases
Solution Approach 1:
The system performs preliminary actions by receiving and storing data beats in the data miss buffer before the complete cache line is available. Storage elements hold incoming data beats from different cache lines, allowing the system to prepare data for future operations without waiting for complete cache lines. This preliminary storage action reduces subsequent memory access latency while maintaining data integrity through proper buffer management.
Solution Approach 2:
The data miss buffer acts as an intermediary between the cache interface and the cache memory, allowing data beats to be temporarily stored and managed before being fully processed. This intermediary buffer enables the system to decouple the data reception from the data processing, allowing data to be received and held without immediate processing requirements, thus reducing latency while ensuring integrity through controlled data flow.
Data Source
AI summary
A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.