Handling Cache Misses in Instruction Boundary Crossing
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Solution Overview
Problem
Modern microprocessors face inefficiencies when fetching instructions that cross cache line boundaries, leading to potential lock-ups due to incomplete instruction retrieval, as current designs lack effective mechanisms to handle cache misses across line boundaries without increasing complexity in the fetch stages and memory resource requests.
Innovation Solution
The solution involves recycling the address of the first part of the instruction back to the fetch pipeline and converting the second part's address into a pre-fetch request, allowing for the loading of necessary instruction data from higher level memory resources without passing it to later stages until both parts are available, thereby ensuring complete instruction retrieval in a single cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor fetches instructions that cross cache line boundaries, then instruction retrieval completeness is improved, but pipeline lock-ups occur due to cache misses
Solution Approach 1:
The patent applies preliminary action by detecting potential cache misses for instructions crossing cache line boundaries before they cause pipeline lock-ups. The system proactively initiates a second fetch operation to retrieve the remaining portion of the instruction from the next cache line, ensuring the complete instruction is available before pipeline execution continues, thus preventing productivity loss while maintaining reliability
2Reliability
If the fetch stage requests data from higher level memories for cache misses, then complete instruction retrieval is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a boundary detection mechanism that identifies when instructions cross cache line boundaries. This intermediary detection layer triggers a controlled second fetch operation only when necessary, rather than implementing complex logic throughout the entire fetch stage. The solution mediates between simple fetch operations and complex cache miss handling by adding a targeted detection and response mechanism, improving reliability without substantially increasing overall device complexity
Data Source
AI summary
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.