Performance Optimization System for Cache Miss Latency Analysis
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Solution Overview
Problem
Existing performance optimization systems fail to identify significant performance impacts despite low cache miss numbers, cannot observe cache misses in processors with external components, and struggle to distinguish bus arbitration latency from genuine access delays.
Innovation Solution
A performance optimization system that includes a required-period-of-time measurement unit, a table entry selection unit, and a cache miss observation unit to measure and classify access delays and latency, allowing for the identification of performance impacts and observation of cache misses even when modifications to the cache memory are not possible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of cache misses is small, then the cache memory performance appears acceptable, but it is impossible to identify cases where the impact on performance is large
Solution Approach 1:
The patent changes the measurement parameter from simple cache miss count to required period of time (latency). By measuring the time duration of cache miss events rather than just counting occurrences, the system can identify performance-critical cache misses even when their frequency is low, thus resolving the contradiction between measurement precision and quantity-based metrics.
2Measurement precision
If modifications are made to the periphery of cache memory to observe cache misses, then cache miss observation becomes possible, but it becomes impossible when processor components are supplied from outside suppliers
Solution Approach 1:
The patent introduces an intermediary approach by observing bus accesses instead of directly accessing cache memory periphery. The bus access observation unit monitors the bus transactions that precede cache accesses, allowing cache miss detection through indirect observation of bus master access patterns without requiring modifications to the cache memory or its immediate periphery, thus maintaining compatibility with externally supplied processors.
3Measurement precision
If bus access timing is observed to measure access delays, then genuine access delays can be measured, but it becomes impossible to distinguish latency caused by bus arbitration from genuine access delays
Solution Approach 1:
The patent segments the latency measurement into two distinct components: bus arbitration latency and genuine cache access latency. By using separate measurement mechanisms (bus arbitration period measurement unit for arbitration latency and required period of time measurement unit for access latency) and separate table entries to store these values, the system can distinguish and analyze each latency source independently, preventing information loss about the origin of delays.
Data Source
AI summary
Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access.