Cache Miss Estimation via Loop Variable Expressions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Researchers face challenges in efficiently acquiring cache miss information during program execution in high-performance computing systems, as existing methods either require prolonged use of real machines or suffer from low execution speeds when using simulators.
Innovation Solution
A method for cache miss estimation is developed, involving the generation of expressions to calculate the number of cache hits and misses based on loop variables and data access patterns, allowing for efficient estimation without requiring extensive real machine usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a simulator is used to create profile data, then the researcher may acquire the profile data without using the HPC system for a long period of time, but the execution speed of the simulator may be significantly lower than the execution speed of the real machine
Solution Approach 1:
The patent creates a simplified simulation model that copies only the essential cache behavior characteristics of the real machine, rather than fully simulating the entire system. This allows profile data to be acquired quickly while maintaining accuracy for cache miss estimation.
Solution Approach 2:
The patent changes the simulation parameters by focusing only on cache-related metrics and behaviors rather than attempting to simulate all system operations. This selective parameter approach accelerates execution while preserving the ability to accurately estimate cache misses.
2Productivity
If the real machine is used to create profile data, then the execution speed is high, but the researcher may not sufficiently create the profile data depending on constraints of time or the like
Solution Approach 1:
The patent creates a simplified simulation model that copies only the essential cache behavior characteristics of the real machine, rather than fully simulating the entire system. This allows profile data to be acquired quickly while maintaining accuracy for cache miss estimation.
Solution Approach 2:
The patent performs preliminary analysis to identify which cache behaviors are most critical for the specific application, then pre-configures the simulation model to focus on those aspects. This preliminary preparation enables faster profile data creation while maintaining accuracy.
3Measurement precision
If a full simulation of cache behavior is performed, then accurate cache miss information can be obtained, but the computational complexity and execution time increase significantly
Solution Approach 1:
The patent extracts only the essential cache behavior characteristics needed for accurate miss estimation, separating these from the full cache simulation. By taking out only the critical elements (access patterns, hit/miss conditions, cache line behaviors), the system achieves accuracy without full simulation complexity.
Solution Approach 2:
The patent segments the cache analysis into distinct components: access pattern detection, cache state modeling, and miss estimation. This segmentation allows each component to be processed independently with optimized algorithms, reducing overall computational complexity while maintaining precision.
Data Source
AI summary
A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.