Cache with Mode Register for Selective Invalidation
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Solution Overview
Problem
The reassignment of cells between virtual machines in data processing systems is time-consuming and inefficient due to the need for power-down and power-up processes, which involve transferring modified data and invalidating cache contents.
Innovation Solution
A cache arrangement with a mode register controlled by a maintenance processor that allows for selective writing and invalidation of cache contents, enabling efficient shut-down or reassignment by distinguishing between modified and unmodified data, and optionally invalidating all cache information for secure reassignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache is cleared by invalidating all cache lines during cell reassignment, then data security between virtual machines is improved, but the time and complexity of reassignment increases
Solution Approach 1:
The cache invalidation process is segmented into two distinct modes: a first mode that invalidates all cache lines for security during virtual machine reassignment, and a second mode that retains unmodified cache lines. The mode register divides the cache management into separate operational paths, allowing selective invalidation based on the specific reassignment scenario.
Solution Approach 2:
The system dynamically switches between two invalidation behaviors based on the state of the mode register. When the mode register indicates a security-critical reassignment, the cache controller invalidates all lines; when indicating a standard reassignment, it preserves unmodified lines. This dynamic adaptation allows the system to optimize between security and performance based on operational context.
2Reliability
If all cache information is invalidated during reassignment, then data integrity for the next virtual machine is improved, but the complexity of the reassignment process increases
Solution Approach 1:
The mode register is pre-configured with the appropriate invalidation mode before the reassignment process begins. This preliminary setup allows the cache controller to automatically execute the correct invalidation strategy without requiring complex runtime decision-making or additional control logic during the actual reassignment operation.
Solution Approach 2:
The complexity of deciding what to invalidate is extracted from the reassignment process itself and encapsulated in the mode register. The mode register serves as a pre-computed control parameter that simplifies the reassignment logic to a straightforward conditional operation based on its state, separating the decision-making complexity from the execution complexity.
3Reliability
If modified data is transferred to main memory during cache shutdown, then data loss is prevented, but the shutdown time increases
Solution Approach 1:
The cache controller automatically identifies and transfers modified cache lines to main memory during shutdown without requiring external intervention or complex coordination. The system self-manages the data preservation process by monitoring the modified bit status of each cache line and initiating transfers only for those lines that require persistence, optimizing the shutdown process.
Data Source
AI summary
A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of first and second values. The controller selectively writes all of the modified information in the cache memory to the system memory responsive to the command. Also in response to this command, all of the information is invalidated in the cache memory if the mode register is set to the second value. In one embodiment, none of the information except the modified data is invalidated if the mode register is set to the first value. The second value may be utilized to efficiently reassign one or more cache memories to a new partition.