Cache Memory Monopoly Sections for Multi-Device Data Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in managing cache memory during program operations, particularly in portable electronic devices, where cache memory is not effectively utilized across multiple program sections, leading to potential data storage failures and increased memory capacity requirements.
Innovation Solution
A memory system design that includes a cache memory shared by multiple memory devices, with specific monopoly sections for each device, allowing temporary storage and data correction units to scramble and descramble data, ensuring efficient data transfer and storage across non-overlapping monopoly sections, thereby enabling proper program operations while reducing cache memory capacity needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache memory is shared by multiple memory devices without monopoly sections, then cache memory utilization is improved, but data storage reliability deteriorates due to potential conflicts and interference
Solution Approach 1:
The patent divides the cache memory access rights into separate monopoly sections for different memory devices. Each device has a dedicated time period during which it exclusively accesses the cache memory, eliminating conflicts while maintaining high utilization through coordinated sharing across devices.
2Reliability
If cache memory capacity is increased to handle multiple program operations, then data storage reliability is improved, but device complexity and cost worsen
Solution Approach 1:
The patent implements dynamic time-based allocation of cache memory access rights. Instead of statically assigning cache memory to individual devices, the system dynamically grants monopoly sections to different devices based on their program operation timing, allowing the same cache memory to serve multiple devices reliably without increasing capacity.
3Speed
If monopoly sections are set to overlap for different memory devices, then program operation speed is improved, but cache memory management complexity worsens
Solution Approach 1:
The patent establishes periodic, non-overlapping monopoly sections for different memory devices. Each device operates during its assigned periodic time window with exclusive cache memory access, enabling parallel program operations at high speed while simplifying management through regular, predictable access patterns rather than complex real-time arbitration.
Data Source
AI summary
A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.