System Cache Peak Power Management via Multi-Burst Precharge

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Solution Overview

Problem

Conventional memory devices face inefficiencies in peak power management due to lack of effective division and regulation of power components, leading to suboptimal performance in managing peak power demand.

Innovation Solution

The implementation of multi-burst precharge techniques in system cache circuitry, utilizing sense amplifiers and precharge blocks arranged in arrays with delayed precharge bursts to spread out charge current, allowing for efficient peak power management in memory applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional power management designs are used in memory devices, then the overall peak demand on the power supply is reduced through regulation, but the performance and efficiency of integrated power designs are suboptimal due to lack of effective division and regulation of power components

Engineering Contradiction:
Improvepeak power managementVSAvoidperformance and efficiency
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent divides the sense amplifier array into multiple independent segments (first sense amplifiers and second sense amplifiers) that can be precharged in separate bursts. This segmentation allows the power demand to be distributed across multiple time intervals rather than concentrated in a single peak, thereby improving both peak power management and overall system efficiency by enabling more effective power component regulation

Inventive Principle:
Principle #1Segmentation

2Power

If multi-burst precharge techniques are implemented to spread out charge current, then peak power management is enhanced and stress on power supply is reduced, but the device complexity increases due to additional delay blocks and control logic

Engineering Contradiction:
Improvepeak current demand distributionVSAvoidcircuit structure
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The sense amplifier array is segmented into multiple groups that can be precharged independently in different bursts. This segmentation enables peak current demand to be distributed across multiple time intervals, reducing instantaneous power stress while maintaining a relatively simple overall circuit structure through systematic organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic precharge bursts with different delay intervals for different sense amplifier groups. By using periodic action with controlled timing, the system spreads out charge current to enhance peak power management without requiring complex continuous control logic, as the periodic nature provides inherent structure and predictability

Inventive Principle:
Principle #19Periodic action

3Duration of action of moving object

If all sense amplifiers are precharged simultaneously in a single burst, then the precharge operation is completed quickly, but the peak current demand creates excessive stress on the power supply

Engineering Contradiction:
Improveprecharge operation timeVSAvoidpeak current demand
Core Design Contradiction:
Duration of action of moving objectVSPower

Solution Approach 1:

Instead of a single simultaneous precharge operation, the patent employs multiple periodic precharge bursts with different timing delays for different sense amplifier groups. This periodic approach distributes the peak current demand across multiple time intervals while maintaining efficient precharge completion, thereby reducing power supply stress without significantly extending total operation time

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11935580B2System cache peak power management
Publication Date: 2024.03.19 ARM LTD
  • US11935580B2 patent drawing
  • US11935580B2 patent drawing
  • US11935580B2 patent drawing

AI summary

One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.