Cache Memory Direct Write to NAND Flash via Register Ranges

Solution Overview

Problem

Existing cache memory systems face challenges in reducing cost and circuit area, as they often require additional memory components to handle cache misses, which increases operational expenses and physical space.

Innovation Solution

A data write system and method that directly writes data from a NAND flash memory to a cache memory upon a cache miss, eliminating the need for additional memory components like dynamic random access memory, by using registers to define ranges and efficiently manage data transfer between the processor circuit, cache memory, and NAND flash memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional memory components (dynamic random access memory) are disposed to handle cache misses, then the reliability and operational capability of the cache memory system is improved, but the cost and circuit area increase

Engineering Contradiction:

Improvecache memory operational capabilityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the functions of the cache memory and the additional memory by enabling the cache memory to directly write data to the NAND flash memory when a cache miss occurs. This eliminates the need for separate dynamic random access memory components, as the cache memory system itself handles both caching and persistent storage functions through the write-through mechanism implemented by the controller.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The cache memory system is designed to perform multiple functions: it acts as both a high-speed cache for frequent data access and a write-through buffer for persistent storage operations. The controller enables the cache memory to directly interface with the NAND flash memory, allowing the same memory structure to serve dual purposes without requiring dedicated additional memory components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional memory components (dynamic random access memory) are disposed to handle cache misses, then the reliability and operational capability of the cache memory system is improved, but the cost increases

Engineering Contradiction:

Improvecache memory operational capabilityVSAvoidcost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the functions of the cache memory and the additional memory by enabling the cache memory to directly write data to the NAND flash memory when a cache miss occurs. This eliminates the need for separate dynamic random access memory components, as the cache memory system itself handles both caching and persistent storage functions through the write-through mechanism implemented by the controller.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The cache memory system is designed to perform multiple functions: it acts as both a high-speed cache for frequent data access and a write-through buffer for persistent storage operations. The controller enables the cache memory to directly interface with the NAND flash memory, allowing the same memory structure to serve dual purposes without requiring dedicated additional memory components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If data is written from NAND flash memory directly to cache memory upon cache miss, then the circuit area is reduced by eliminating additional memory, but the data transfer complexity increases

Engineering Contradiction:

Improvecircuit areaVSAvoiddata transfer control

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The controller serves as an intermediary that manages the direct data transfer between the NAND flash memory and the cache memory. It handles the complexity of data transfer by implementing the write-through logic, determining when cache misses occur, and orchestrating the data flow between storage devices, thereby simplifying the overall system architecture while managing transfer complexity centrally.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The cache memory system is designed to perform multiple functions: it acts as both a high-speed cache for frequent data access and a write-through buffer for persistent storage operations. The controller enables the cache memory to directly interface with the NAND flash memory, allowing the same memory structure to serve dual purposes without requiring dedicated additional memory components.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11500776B2Data write system and method with registers defining address range

Publication Date: 2022.11.15 REALTEK SEMICON CORP

AI summary

A data write system includes a processor circuit, a first memory, at least one register, and a second memory. The first memory is coupled to the processor circuit. The at least one register is configured to define at least one range. The second memory is coupled to the first memory. If a cache miss occurs and an access address of a reading command is in the at least one range in the second memory, a predetermined amount of data corresponding to the access address is written from the second memory into at least one first way of the first memory.