Write-back Cache Object Aggregation for Memory Bandwidth Optimization

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Solution Overview

Problem

Current cloud computing systems face inefficiencies in network speed due to the high number of memory accesses required for write-back operations in network devices, particularly when handling small objects, which leads to reduced bandwidth and increased latency.

Innovation Solution

Implementing a write-back engine that aggregates close objects for a single read-modify-write operation in external memory, reducing the number of memory accesses and improving bandwidth by grouping objects within cache lines for simultaneous processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate read-modify-write operations are performed for each small object in external memory, then object update reliability is improved, but memory bandwidth and network speed deteriorate due to excessive memory accesses

Engineering Contradiction:
Improveobject update reliabilityVSAvoidmemory bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple separate read-modify-write operations into a single aggregated operation. Multiple small objects (e.g., counters) that need to be updated are grouped together and processed in a single memory transaction, reducing the total number of memory accesses while maintaining update reliability for each object.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary aggregation of objects to be updated before executing the write-back operation. Objects are collected and grouped by their memory line locations in advance, allowing the subsequent memory operation to process multiple objects simultaneously in a single read-modify-write cycle.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If separate read-modify-write operations are performed for each small object, then update precision is maintained, but latency increases due to multiple sequential memory accesses

Engineering Contradiction:
Improveupdate precisionVSAvoidwrite-back latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Multiple sequential memory accesses are merged into a single parallel operation. By grouping multiple small objects that reside in the same or adjacent memory lines, the system performs read-modify-write operations for all objects simultaneously, reducing latency while preserving the precision of individual updates through proper atomic operation handling.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary grouping and sorting of objects to be updated based on their memory locations before executing the write-back. This preliminary organization enables the memory controller to issue a single consolidated read-modify-write operation that updates all objects in parallel, minimizing the time spent on sequential accesses.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If full memory lines are read and written for each small object, then memory access completeness is ensured, but device complexity increases due to repeated access patterns

Engineering Contradiction:
Improvememory access completenessVSAvoidmemory access complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple repeated memory access patterns into a single unified operation. Instead of separately reading and writing full memory lines for each small object, the system aggregates these access patterns and executes a single read-modify-write operation that handles all objects, reducing the complexity of the memory access logic while ensuring completeness through proper line-based operations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230129107A1Method and apparatus to aggregate objects to be stored in a memory to optimize the memory bandwidth
Publication Date: 2023.04.27 INTEL CORP
  • US20230129107A1 patent drawing
  • US20230129107A1 patent drawing
  • US20230129107A1 patent drawing

AI summary

A network device performs packet processing operations on packets received from a network and includes a write back cache to store data (for example, counters) used to perform the packet processing operations. The data stored in the write cache in the network device are evicted from the write back cache to an external memory from time to time using a write-back operation that includes a read-modify-write of a line in the external memory. Instead of performing a separate read-modify-write for each data stored in the cache line, a single read-modify-write operation is performed for all data stored in the cache line in the write back cache. The aggregation of relatively close data for the single read-modify-write operation reduces the number of memory accesses to the external memory and improves the bandwidth to the external memory.