Set-Associative Cache Occupancy Bits for Faster Memory Access
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Solution Overview
Problem
Existing processor caches, particularly N-way set associative caches, suffer from inefficiencies in memory operations due to the need for costly and power-consuming way-by-way searches during write and read operations, leading to thrashing and conflict misses.
Innovation Solution
Implementing occupancy state information for N-way set associative caches to determine whether a set is full or empty before scanning, using full-bits or empty-bits to avoid unnecessary searches, thereby reducing clock cycles and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the cache scans all ways of a set to determine availability for memory operations, then it can accurately identify empty cache lines, but it increases clock cycles and power consumption
Solution Approach 1:
The patent applies preliminary action by maintaining occupancy state information (full-bit and empty-bit) in advance within the cache structure. These bits are updated whenever cache lines are allocated or evicted, so that when a memory operation needs to determine set availability, the cache already has the occupancy status ready without needing to scan all ways. This pre-computed state information eliminates the time-consuming scanning process while maintaining accurate occupancy determination.
2Measurement precision
If the cache scans all ways of a set to determine availability for memory operations, then it can accurately identify empty cache lines, but it increases power consumption
Solution Approach 1:
The patent applies preliminary action by maintaining occupancy state information (full-bit and empty-bit) in advance within the cache structure. These bits are updated whenever cache lines are allocated or evicted, so that when a memory operation needs to determine set availability, the cache already has the occupancy status ready without needing to scan all ways. This pre-computed state information eliminates the time-consuming scanning process while maintaining accurate occupancy determination.
3Productivity
If the cache maintains occupancy state information for each set, then it can perform memory operations without scanning all ways, but it increases device complexity
Solution Approach 1:
The patent applies local quality by adding occupancy state information (full-bit and empty-bit) at the set level rather than requiring global scanning of the entire cache. Each set maintains its own occupancy bits independently, allowing memory operations to quickly determine availability of specific sets without affecting or being affected by other sets. This localized approach minimizes the impact on overall cache complexity while significantly improving memory operation efficiency.
Data Source
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AI summary
Various example embodiments for supporting operation of a processor cache are presented herein. Various example embodiments for supporting operation of a processor cache may be configured to support operation of an N-way set associative cache based on occupancy state information. Various example embodiments for supporting operation of an N-way set associative cache may be configured to support operation of the N-way set associative cache based on occupancy state information where the occupancy state information may be used to support more efficient memory operations on the N-way set associative cache. Various example embodiments for supporting operation of an N-way set associative cache based on occupancy state information may be configured to maintain occupancy state information for a set of the N-way set associative cache to support more efficient memory operations, including write operations and read operations, on the N-way set associative cache.