Dynamic Cache Ownership Remapping in Clustered Multiprocessors
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Solution Overview
Problem
Traditional chip multiprocessor (CMP) architectures face performance issues due to coherency challenges and significant delays when changes occur in address hash functions, leading to cache flushes and quiescence of entire CMPs, which are inefficient and impact performance.
Innovation Solution
Implementing a dynamic cache hash change mechanism that remaps cache lines between clusters and updates directory information to manage cache ownership changes without quiescing the entire CMP, allowing for efficient handling of address hash changes and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address hash function changes are implemented in traditional CMP architectures, then cache ownership can be updated, but the entire CMP must be quiesced and cache flushes must be executed, causing significant performance delays
Solution Approach 1:
The patent segments the cache system into owner clusters and non-owner clusters, allowing independent management of cache ownership. When an address hash function change occurs, only the affected owner cluster is quiesced and updated, while other clusters continue operating normally. This segmentation eliminates the need to quiesce the entire CMP, reducing the time loss from milliseconds to much shorter durations localized to specific clusters.
2Adaptability or versatility
If distributed cache is shared by multiple cores to optimize cache usage, then cache flexibility is improved, but coherency challenges increase significantly
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a directory structure that tracks cache line ownership and location. This directory acts as a mediator between multiple cores and the distributed cache, providing a centralized view of cache state without requiring complex peer-to-peer coherency protocols. The directory enables efficient ownership transfer and coherency maintenance, reducing the overall complexity of managing shared distributed cache across multiple cores.
Data Source
AI summary
A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.