Cache Padding for Overfetching Reduction

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Solution Overview

Problem

Existing cache systems experience overfetching issues due to unused holes in cache lines after compression, leading to inefficient bandwidth usage and increased power consumption as irrelevant data is fetched and written back to main memory.

Innovation Solution

Implementing a supplemental write command that fills cache lines with padding data, such as constant values or patterns, to eliminate overfetching by ensuring only compressed data is retrieved from main memory, reducing bandwidth and power requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If compression is applied to reduce data size, then bandwidth efficiency is improved, but cache line utilization deteriorates due to unused holes

Engineering Contradiction:
Improvedata sizeVSAvoidcache line utilization
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent converts the harmful effect of unused cache space into a beneficial feature by injecting padding hints that serve dual purposes: filling the unused space and providing compression metadata. This transforms the waste space into useful information carriers that enable better compression ratios and cache utilization simultaneously.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent merges the padding function with the hint function by combining compression metadata and padding data into a single integrated structure within the cache line. This consolidation eliminates separate overhead and maximizes the utilization of available cache space for multiple purposes.

Inventive Principle:
Principle #5Merging (Combining)

2Loss of energy

If cache lines are filled with padding data, then overfetching is reduced, but additional processing complexity is introduced

Engineering Contradiction:
Improvepower consumptionVSAvoidcache control complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent performs padding injection at the time of cache line population, before the data is stored in the cache. This preliminary action ensures that when data is later fetched from main memory, the cache lines are already properly padded, eliminating the need for runtime padding operations and reducing overall system complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The compression engine itself performs the padding injection as part of its normal compression operation, without requiring a separate padding module or additional control logic. This self-service approach minimizes added complexity while achieving the padding objective.

Inventive Principle:
Principle #25Self-service

3Productivity

If variable width hints are injected into cache lines, then compression efficiency is improved, but cache line management complexity increases

Engineering Contradiction:
Improvecompression efficiencyVSAvoidhint management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements variable-width hint fields that dynamically adjust their size based on the actual compression ratio achieved. This dynamic structure allows the hint width to expand or contract as needed, optimizing space utilization while maintaining the ability to convey sufficient compression metadata for different data types and compression levels.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3183659B1Power aware padding
Publication Date: 2018.01.10 QUALCOMM INC
  • EP3183659B1 patent drawingFigure 1
  • EP3183659B1 patent drawingFigure 2~3
  • EP3183659B1 patent drawingFigure 4~5

AI summary

Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.