Cache Page Copy in Non-Volatile Memory
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in efficiently utilizing resources for high-capacity and high-performance memory operations, particularly in efficiently relocating and programming multi-bit data across memory cells with minimal latency and power consumption.
Innovation Solution
The implementation of a cache page copy scheme that uses a minimum of n+1 data latches per memory cell, allowing for efficient data relocation and read operations with compensation for adjacent word line data, enabling adaptive full-sequence programming and look-ahead correction to minimize data processing time and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data relocation methods are used in non-volatile memory, then data can be copied between memory locations, but the process requires waiting for all code bits to be available before programming, increasing data processing time and reducing productivity
Solution Approach 1:
The patent applies preliminary action by reading and latching data from the source memory location before the programming operation is complete. Specifically, while programming is ongoing, the system reads the next page of data and latches it in buffer latches, so that when programming finishes, the next data is already ready. This eliminates waiting time and allows continuous operation, improving productivity while reducing data processing time.
2Productivity
If sufficient data latches are provided to buffer all code bits simultaneously, then data processing can proceed in parallel, but the device complexity and resource requirements increase significantly
Solution Approach 1:
The patent segments the data buffering process into multiple stages using different types of latches: read latches hold data during reading, buffer latches hold data during programming, and buffer2 latches hold data during verification. This segmentation allows the system to use a minimal number of latches (n+1 per memory cell) by reusing them across different operation phases, reducing device complexity while maintaining high data processing throughput through pipelined operations.
Solution Approach 2:
The patent implements nested doll by organizing latch structures in hierarchical levels where read latches, buffer latches, and buffer2 latches are nested within the overall data path. The buffer latches are further nested with buffer2 latches, allowing data to flow through multiple processing stages using the same physical latch resources at different times. This nesting minimizes the total number of latches required while enabling complex data processing operations.
3Speed
If data is read and processed sequentially waiting for complete code availability, then resource usage is minimized, but programming latency increases and overall memory operation speed decreases
Solution Approach 1:
The patent achieves continuity of useful action by implementing a pipelined data flow where reading, latching, and programming operations overlap in time. While one page of data is being programmed, the next page is being read and latched in buffer latches. This continuous operation eliminates idle time between programming cycles, significantly increasing programming speed without requiring a complex array of simultaneous buffers, as the same latches are reused in a time-multiplexed fashion.
Data Source
AI summary
A non-volatile memory and methods includes cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line.