Compressed Cache Hardware Decompression for Faster Page Fault Recovery
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Solution Overview
Problem
Current compressed cache technologies face latency issues during page faults due to serialized operations, limiting the aggressiveness of page swapping and memory utilization in computing systems, which can lead to performance penalties and increased costs.
Innovation Solution
Implementing a hardware decompression accelerator and parallel decompression techniques to overlap decompression operations with other processing steps, allowing for reduced latency and more aggressive swapping to a compressed cache, thereby enhancing memory utilization and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If software-based compression is used in compressed cache, then memory utilization is improved, but page fault processing latency increases due to serialized operations
Solution Approach 1:
The patent replaces software-based compression with a hardware decompression accelerator that operates in parallel. This substitution transforms the serialized software processing into parallel hardware processing, significantly reducing page fault latency while maintaining memory utilization benefits.
Solution Approach 2:
The patent implements decompression on fault by pre-positioning compressed pages in the compressed cache before they are needed. When a page fault occurs, the hardware accelerator immediately begins decompression in parallel with other processing steps, eliminating the need for sequential waiting.
2Quantity of substance
If aggressive page swapping is implemented, then memory availability is improved, but system performance deteriorates due to increased page fault latency
Solution Approach 1:
By replacing software compression with hardware acceleration, the system can afford to be more aggressive with page swapping to the compressed cache. The parallel hardware decompression ensures that performance is not degraded despite increased swapping activity.
3Device complexity
If serialized decompression operations are used, then device complexity is reduced, but processing speed deteriorates
Solution Approach 1:
The patent prepares decompression work descriptors in advance and positions compressed pages in the compressed cache before they are needed. This preliminary preparation enables parallel processing when page faults occur, dramatically improving processing speed without excessive complexity.
Data Source
Figure 1A~1B
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Figure 3B
AI summary
An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.