Cache Page Refactoring for Parallel IO and Latency Reduction

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Solution Overview

Problem

Existing data storage systems face inefficiencies in handling parallel IO requests due to alignment issues and range lock contention, leading to serial execution of IO operations and increased latency.

Innovation Solution

Refactoring cache pages into smaller cache units based on the alignment pattern and length of IO requests, with the use of bitmaps to indicate valid and dirty units, allowing for parallel execution and selective flushing of dirty units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache pages are used for data storage, then data availability is improved, but parallel IO request execution is hindered due to alignment issues and range lock contention

Engineering Contradiction:
Improvedata availabilityVSAvoidparallel IO request execution
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides cache pages into smaller cache units (e.g., 4KB units from 8KB pages) and introduces bitmaps to track the state of each unit. This segmentation allows parallel IO requests to operate on specific cache units without acquiring locks on entire cache pages, enabling fine-grained concurrency control and eliminating the bottleneck of range lock contention while preserving data availability through the cache system.

Inventive Principle:
Principle #1Segmentation

2Productivity

If IO requests are executed in parallel, then productivity is improved, but alignment issues cause execution inefficiency and increased latency

Engineering Contradiction:
ImproveIO request execution speedVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies local quality by treating different portions of cache pages differently through the bitmap mechanism. Each cache unit within a page can have its own validity and dirty status tracked independently, allowing the system to process only the specific units needed by each IO request. This eliminates wasted time processing aligned but unnecessary data and reduces latency by enabling true parallel execution of misaligned IO requests on different cache units.

Inventive Principle:
Principle #3Local quality

3Reliability

If full cache pages are flushed, then data consistency is maintained, but storage device life is reduced due to excessive write operations

Engineering Contradiction:
Improvedata consistencyVSAvoidstorage device life
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent extracts the flushing operation from the cache page level down to the cache unit level using bitmaps. Instead of flushing entire cache pages to maintain consistency, the system identifies and flushes only the specific dirty cache units that need to be written back. This selective flushing dramatically reduces the number of write operations to storage devices, extending their operational life while maintaining data consistency through targeted persistence of modified data.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10747674B2Cache management system and method
Publication Date: 2020.08.18 EMC IP HLDG CO LLC
  • US10747674B2 patent drawing
  • US10747674B2 patent drawing
  • US10747674B2 patent drawing

AI summary

A method, computer program product, and computing system for identifying, at the computing device, one or more cache pages in a cache system. One or more cache pages may be refactored into one or more cache units within the one or more cache pages. A plurality of parallel IO requests may be executed on the one or more cache units within the one or more cache pages.