Multi-level Cache Partitioning for Context Switching

Solution Overview

Problem

Computer systems face challenges in achieving high performance and independent performance design for each function due to the limitations of level-1 cache memory, particularly with increasing processor cores and threads, which often require larger cache capacities, complicating circuit design and increasing costs.

Innovation Solution

A computer system architecture that includes a shared cache memory and a partitioned cache memory, where the partitioned cache memory is used for data accessed by virtual processors, reducing switching losses and allowing for faster data access, thus eliminating the need for high-capacity cache memory and simplifying circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the capacity of level-1 cache memory is increased to accommodate more processor cores and threads, then the system can support more virtual processors, but the circuit design becomes more complex and the operation speed decreases

Engineering Contradiction:

Improvecache memory capacityVSAvoidcircuit design complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The cache memory is divided into a shared cache memory (L1) and a partitioned cache memory (L2). The shared cache memory is kept small and simple for fast access, while the partitioned cache memory is divided into multiple storage areas corresponding to different virtual processors. This segmentation allows the system to support multiple processors without increasing the complexity of the shared cache circuit.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the capacity of level-1 cache memory is increased to accommodate more processor cores and threads, then the system can support more virtual processors, but the operation speed of the cache memory decreases

Engineering Contradiction:

Improvecache memory capacityVSAvoidcache memory operation speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The cache memory is divided into a shared cache memory (L1) and a partitioned cache memory (L2). The shared cache memory is kept small and simple for fast access, while the partitioned cache memory is divided into multiple storage areas corresponding to different virtual processors. This segmentation allows the system to support multiple processors without increasing the complexity of the shared cache circuit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The partitioned cache memory pre-allocates storage areas to different virtual processors before context switching occurs. When a context switch is needed, the system can quickly transfer data between the shared cache and the appropriate partitioned storage area, reducing the time penalty of context switching and maintaining high operation speed.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If context switching between virtual processors is performed with fine granularity, then performance isolation between threads is improved, but switching overhead increases

Engineering Contradiction:

Improveperformance isolationVSAvoidswitching overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The partitioned cache memory pre-allocates storage areas to different virtual processors before context switching occurs. When a context switch is needed, the system can quickly transfer data between the shared cache and the appropriate partitioned storage area, reducing the time penalty of context switching and maintaining high operation speed.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9063794B2Multi-threaded processor context switching with multi-level cache

Publication Date: 2015.06.23 BEIJING ESWIN COMPUTING TECH CO LTD

AI summary

A computer system includes: a main storage unit, a processing executing unit sequentially executing processing to be executed on virtual processors; a level-1 cache memory shared among the virtual processors; a level-2 cache memory including storage areas partitioned based on the number of the virtual processors, the storage areas each (i) corresponding to one of the virtual processors and (ii) holding the data to be used by the corresponding one of the virtual processors; a context memory holding a context item corresponding to the virtual processor; a virtual processor control unit saving and restoring a context item of one of the virtual processors; a level-1 cache control unit; and a level-2 cache control unit.