Cache Partitioning for Performance Monitoring

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Solution Overview

Problem

Current processor systems lack effective mechanisms to dynamically adjust cache management configurations in response to changing workload behaviors, leading to suboptimal performance due to limited hardware adaptive mechanisms that are inflexible and not visible to software.

Innovation Solution

Implementing cache partitioning and performance monitoring using machine-specific registers (MSRs) that allow users and software to customize cache policies and track performance metrics across partitions, enabling dynamic adjustments based on real-time workload changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If hardware adaptive mechanisms are used to manage cache, then cache management automation is improved, but flexibility and software visibility are reduced

Engineering Contradiction:
Improvecache management automationVSAvoidsoftware flexibility
Core Design Contradiction:
Extent of automationVSAdaptability or versatility

Solution Approach 1:

The patent introduces machine-specific registers (MSRs) as an intermediary layer between software and hardware cache mechanisms. These MSRs allow software to read cache performance monitoring information and write cache management configurations, providing visibility and control without directly exposing or complicating the hardware adaptive mechanisms. This mediator enables software to make informed decisions about cache configuration while the hardware continues to operate autonomously with advanced features like demand throttling and set sampling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If cache partitioning with multiple policies is implemented, then cache performance adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvecache policy adaptabilityVSAvoidcache management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the cache into multiple partitions, each capable of having independent cache management policies applied to them. This segmentation allows different parts of the cache to be optimized for different workload characteristics simultaneously. The cache controller maintains separate policy configurations for each partition, enabling fine-grained control over cache behavior without requiring complete redesign of the entire cache management system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables dynamic switching between different cache management policies based on workload characteristics. Through the MSR interface, software can monitor cache performance and adjust partition assignments and policy configurations in response to changing workload demands. This dynamic adaptability allows the cache system to optimize for different access patterns, thread priorities, and memory behaviors without being locked into a single static configuration.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If static cache configuration is used, then device complexity is reduced, but performance optimization capability is limited

Engineering Contradiction:
Improvecache configuration simplicityVSAvoidcache performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements a self-service mechanism where software can autonomously monitor cache performance through MSRs and adjust cache configurations based on observed workload patterns. The performance monitoring information provided through MSRs enables software to automatically tune cache parameters, partition assignments, and policy selections without requiring complex preconfiguration or external intervention. This self-service capability bridges the gap between simple static configuration and complex dynamic management by enabling adaptive optimization through software autonomy.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10482017B2Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization
Publication Date: 2019.11.19 INTEL CORP
  • US10482017B2 patent drawing
  • US10482017B2 patent drawing
  • US10482017B2 patent drawing

AI summary

Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.