Configurable Private-Shared Cache Partitioning for Multi-Core Workloads
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Solution Overview
Problem
Conventional cache designs in microprocessors, particularly in multi-core systems, fail to optimize cache allocation for specific workloads, leading to inefficient utilization of computing resources and lower performance in cloud or hyperscale computing environments.
Innovation Solution
A configurable combined private and shared cache structure that allows dynamic adjustment of the relative sizes of private and shared cache portions based on workload requirements, enabling flexible allocation through firmware configuration or system resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed-size private L2 cache and shared L3 cache are provided for each core, then the cache hierarchy provides stable performance for general workloads, but the cache allocation cannot be optimized for specific workload characteristics, leading to lower overall performance and resource utilization
Solution Approach 1:
The cache configuration is made dynamic and reconfigurable, allowing the private and shared cache sizes to be adjusted based on workload requirements. The configurable combined cache structure enables different allocation scenarios (e.g., 6MB private/2MB shared, 4MB private/4MB shared, 2MB private/6MB shared) to be implemented by modifying the cache way allocation, thereby adapting to various workload characteristics without requiring multiple fixed cache designs.
2Productivity
If multiple applications or virtual machines are run on the same microprocessor, then resource utilization improves, but the static cache hierarchy cannot be efficiently shared among different workloads with different memory access profiles
Solution Approach 1:
The cache parameters (specifically the division of cache ways between private and shared portions) are changed based on the workload requirements. Different workload types can be assigned different cache configurations optimized for their specific memory access patterns, allowing multiple applications or virtual machines with different profiles to run efficiently on the same microprocessor without interfering with each other's performance.
3Adaptability or versatility
If a physically combined cache structure is used, then flexibility in cache allocation is improved, but the complexity of managing and configuring the cache increases
Solution Approach 1:
The physically combined cache is segmented into distinct private and shared portions through logical separation. Each portion can be independently configured and managed, with clear boundaries defined by the allocation of cache ways. This segmentation simplifies the management complexity by providing clear ownership and access rules for each segment while maintaining the flexibility benefits of the combined structure.
Data Source
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AI summary
Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.