Processor Cache Partitioning for Network Packet Processing
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Solution Overview
Problem
Modern network processors face challenges in efficiently processing and securing network protocols across multiple layers (L3-L7) due to cache hierarchy complexities, which affect packet classification, access control, and intrusion detection, leading to increased latency and bandwidth issues.
Innovation Solution
A memory subsystem with a three-level cache hierarchy, including L1 instruction and data caches, a mid-level cache, and a low-level cache controller, optimized for efficient instruction and data management, reduces invalidation commands and improves bandwidth by selectively sending invalidation commands based on cache storage locations, and employs partitioning to manage cache storage efficiently across multiple processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a larger cache is used to improve processing speed, then cache capacity increases, but access latency increases
Solution Approach 1:
The cache is divided into multiple levels (L1, L2, L3) with different capacities and access speeds. L1 cache provides fast access for frequently used data, while L2 and L3 provide larger capacity for less frequently accessed data. This segmentation resolves the contradiction by providing both small fast cache and large slow cache in a hierarchical structure.
Solution Approach 2:
The patent introduces a mid-level cache between L1 and L3 caches, adding an intermediate dimension to the cache hierarchy. This mid-level cache specifically handles instruction caching to reduce invalidation commands, providing a dimensional solution to the latency-capacity tradeoff by placing cache memory at different hierarchical levels.
2Reliability
If invalidation commands are sent to maintain cache coherence, then cache consistency is improved, but communication traffic and bandwidth are increased
Solution Approach 1:
The patent extracts the instruction cache functionality into a separate mid-level cache between L1 and L3 caches. This extracted mid-level instruction cache does not require invalidation commands from L3 to L2, as it independently manages instruction caching. This separation removes the source of invalidation traffic while maintaining cache coherence through selective invalidation only where necessary.
3Productivity
If cache partitioning is implemented to manage multiple processor cores, then cache management efficiency is improved, but device complexity is increased
Solution Approach 1:
The mid-level cache serves multiple functions: it caches instructions for multiple processor cores, reduces invalidation traffic to L3 cache, and maintains cache coherence. This multi-functional design improves cache management efficiency across multiple cores while managing complexity through a unified mid-level cache structure that handles various caching requirements.
Data Source
AI summary
A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.