Processor Cache Partitioning for Translation Entry Allocation
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Solution Overview
Problem
In virtualized cloud environments, the performance of guest applications suffers due to frequent context switching and memory footprint issues, leading to cache and TLB congestion, which results in significant performance overhead and degradation.
Innovation Solution
A processor architecture that intelligently partitions the data cache to allocate space for translation entries, using a dynamic cache partitioning scheme based on monitoring data and translation stack distances and marginal utility principles, separating TLB and data traffic to reduce cache contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data cache is used to cache translation entries to reduce page walk latency, then the translation performance is improved, but the data cache contention increases and data access performance deteriorates
Solution Approach 1:
The patent divides the data cache into two separate ways: data ways for caching data entries and translation ways for caching translation entries. This segmentation allows translation entries to be cached in the data cache without causing contention with data accesses, as the two types of accesses are directed to different ways within the same cache structure.
2Reliability
If the TLB capacity is increased to handle large footprint workloads, then the translation hit rate is improved, but the cache capacity is consumed and data cache performance deteriorates
Solution Approach 1:
By segmenting the data cache into data ways and translation ways, the patent enables the TLB to effectively utilize cache capacity without competing with data accesses. The translation ways are specifically allocated for TLB entries, allowing the TLB to maintain high hit rates even for large footprint workloads while data ways remain dedicated to data caching.
3Productivity
If frequent context switching is performed to achieve high machine utilization, then the resource utilization is improved, but the TLB flush overhead increases and translation performance deteriorates
Solution Approach 1:
The patent extracts the translation entry caching function from the traditional TLB structure and places it within the data cache using dedicated translation ways. This extraction allows context switching to proceed without flushing translation entries, as the translation ways can be independently managed and do not interfere with the context switching process, thereby eliminating TLB flush overhead.
4Loss of time
If the page walk is optimized by caching intermediate entries in the data cache, then the page walk latency is reduced, but the data cache capacity is consumed and data access performance deteriorates
Solution Approach 1:
The patent segments the data cache into data ways and translation ways, allowing intermediate page walk entries to be cached in the translation ways without interfering with data access performance. This segmentation enables the system to reduce page walk latency by caching intermediate entries while preserving data access performance through dedicated data ways.
Data Source
AI summary
A processor architecture which partitions on-chip data caches to efficiently cache translation entries alongside data which reduces conflicts between virtual to physical address translation and data accesses. The architecture includes processor cores that include a first level translation lookaside buffer (TLB) and a second level TLB located either internally within each processor core or shared across the processor cores. Furthermore, the architecture includes a second level data cache (e.g., located either internally within each processor core or shared across the processor cores) partitioned to store both data and translation entries. Furthermore, the architecture includes a third level data cache connected to the processor cores, where the third level data cache is partitioned to store both data and translation entries. The third level data cache is shared across the processor cores. The processor architecture can also include a data stack distance profiler and a translation stack distance profiler.