Cache Pollution Mitigation via Multi-Level Reuse Information
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Solution Overview
Problem
Cache pollution occurs in computing systems where cache lines with lower reusability displace those with higher reusability, particularly in virtualized environments where guest operating systems lack direct control over physical address layouts, making it difficult to effectively mitigate cache pollution using traditional techniques like page coloring.
Innovation Solution
The method involves managing address translation and caching by determining reuse information at multiple access levels, including virtual and physical address spaces, and processing this information to store cache lines in selected portions of the cache, allowing for flexible selection and combination of reuse information to optimize cache line placement without relying on special address assignments or interference with address translation schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional page coloring techniques are used to mitigate cache pollution, then cache lines with high reusability are preserved, but guest operating systems require direct control over physical address layouts which is not available in virtualized environments
Solution Approach 1:
The patent introduces an intermediary mechanism (the pollute buffer and associated control logic) that mediates between the guest operating system's cache access requests and the physical address space. This intermediary allows the system to mitigate cache pollution without requiring the guest OS to have direct control over physical address layouts, resolving the contradiction between maintaining cache line reusability and adapting to virtualized environments where address control is restricted.
Solution Approach 2:
The cache is segmented into a main cache portion and a pollute buffer portion. The pollute buffer is specifically designated to store cache lines with low reusability, while the main cache preserves high reusability cache lines. This segmentation allows the system to maintain high cache efficiency without requiring guest OS control over physical addresses, as the pollute buffer automatically captures problematic cache lines.
2Productivity
If cache lines with low reusability are allowed to displace high reusability cache lines, then cache space is freely available, but cache pollution occurs reducing overall system performance
Solution Approach 1:
The patent converts the harmful effect of low reusability cache lines into a beneficial mechanism by using them as indicators to populate the pollute buffer. Instead of allowing these cache lines to pollute the main cache and reduce productivity, the system identifies them and isolates them in the pollute buffer, thereby protecting the main cache and maintaining high cache access efficiency while preventing cache pollution.
Solution Approach 2:
The patent extracts cache lines with low reusability from the main cache and places them in a separate pollute buffer. This extraction prevents low reusability cache lines from displacing high reusability cache lines in the main cache, thereby maintaining cache access efficiency while removing the harmful factor of cache pollution from the main cache structure.
3Measurement precision
If multiple translation stages are implemented to determine reuse information, then cache management precision is improved, but system complexity increases
Solution Approach 1:
The patent implements preliminary action by determining reuse information at multiple translation stages (virtual to intermediate physical, then intermediate physical to physical) before cache line placement decisions are made. This preliminary determination of reuse characteristics at each translation stage allows for precise cache management without adding complexity to the actual cache operation, as the reuse information is prepared in advance and used to guide cache line placement in the pollute buffer or main cache.
Data Source
AI summary
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.