Cache Port Utilization Circuitry for SoC Pre-fetch Latency
Solution Overview
Problem
Conventional System on a Chip (SoC) architectures face inefficiencies in cache pre-fetch operations due to the need for dedicated ports for fetching and pre-fetching instructions and data, which can lead to increased latency and complexity in communication between the processing core, cache, and memory.
Innovation Solution
The implementation of a port utilization circuitry that selectively uses cache instruction and data ports for both fetching and pre-fetching operations, allowing simultaneous or overlapping requests to be transmitted through these ports to optimize resource utilization and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated ports are used for fetching and pre-fetching instructions and data, then communication reliability is improved, but device complexity and latency increase
Solution Approach 1:
The cache instruction port and data port are designed to handle multiple functions: both fetching and pre-fetching operations can occur through the same ports. The port utilization circuitry dynamically determines whether each port is available for pre-fetching based on current usage state, allowing one port to serve multiple purposes without dedicated separate ports for each function.
Solution Approach 2:
The patent combines the functions of fetching and pre-fetching operations into shared ports. Instead of having separate dedicated ports for each operation type, the instruction port and data port are merged to handle both current and pre-fetch requests, reducing the total number of ports required while maintaining operational reliability through the port utilization circuitry.
2Reliability
If dedicated ports are used for fetching and pre-fetching instructions and data, then communication reliability is improved, but latency increases
Solution Approach 1:
The system performs pre-fetching operations in advance of actual data needs. The port utilization circuitry identifies when ports become available and initiates pre-fetch requests for instructions or data that are likely to be needed soon, allowing the processing core to receive data without waiting for full memory access cycles.
Solution Approach 2:
The port utilization circuitry continuously monitors port availability and dynamically switches between fetching and pre-fetching operations to keep ports actively utilized. This continuous operation eliminates idle time between fetch cycles and overlaps pre-fetch operations with current fetch operations to maintain constant productive activity.
3Device complexity
If shared ports are used for fetching and pre-fetching, then device complexity is reduced, but port availability and fetching reliability may worsen
Solution Approach 1:
The port utilization circuitry dynamically determines port availability in real-time based on current operation state. Rather than static port allocation, the system adaptively switches port usage between fetching and pre-fetching modes, monitoring whether a port is currently engaged in a fetch operation before allowing pre-fetch requests to use that same port.
Solution Approach 2:
The port utilization circuitry implements feedback mechanisms to monitor port usage state and adjust pre-fetch timing accordingly. When a port is determined to be unavailable for pre-fetching, the circuitry waits or redirects the request, ensuring that pre-fetch operations do not interfere with active fetch operations and maintaining overall system reliability.
Data Source
AI summary
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.