Hardware Dynamic Cache Power Management via Bridge Control
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Solution Overview
Problem
In digital systems, particularly in integrated circuits of mobile devices, power management is critical due to increasing transistor counts, leading to high power consumption and heat generation, which existing methods like clock gating and power gating struggle to efficiently manage, especially when processors are powered down and software is not executable.
Innovation Solution
A control circuit is configured to transmit operations to a circuit block for reinitialization during power up or down, allowing the cache to be powered up or down independently of processors, using a bridge that couples peripherals and peripheral interface controllers to the cache, and storing operations in memory for execution before or after power changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is used to reduce leakage current to near zero, then power consumption is reduced, but the circuit block requires reinitialization which must be handled by software executed on a processor
Solution Approach 1:
The patent stores reinitialization operations in a memory (register file) before power gating occurs. When the circuit block is powered back up, these pre-stored operations are automatically transmitted to reinitialize the block, eliminating the need for software intervention and allowing power gating to occur even when processors are powered down.
2Loss of energy
If the cache is powered down to reduce power consumption, then power and heat are reduced, but the cache cannot be powered up during processor downtime without waking the processors
Solution Approach 1:
The patent segments the cache into two independently controllable parts: the cache control circuitry and the cache memory. The control circuitry can be powered down to save power while the cache memory remains powered to retain data. This segmentation allows the cache to be partially powered down without completely disabling cache operations, enabling peripheral memory operations to proceed even when processors are powered down.
3Reliability
If processors are kept powered on to handle cache reinitialization, then reinitialization can be performed, but battery life is reduced and heat generation increases
Solution Approach 1:
The patent implements a self-service mechanism where the bridge contains control circuitry that automatically transmits pre-stored reinitialization operations from memory to the cache control circuitry when power is restored. This automated hardware-based reinitialization eliminates the need for processor intervention, allowing processors to be powered down completely while still enabling cache reinitialization when needed, thereby extending battery life and reducing heat generation.
Data Source
AI summary
In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.