Cache-Region Power Connection Lines for Stable Multi-Core Voltage

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Solution Overview

Problem

Semiconductor devices face challenges in stably supplying operating voltage to multiple cores and power domains due to physical separation, leading to excessive heat generation and instability in power delivery.

Innovation Solution

Incorporating power connection lines that connect physically separated power lines within the same power domain, allowing for stable voltage supply across cores and domains, and utilizing a power management integrated circuit with voltage regulator modules to generate and transmit operating voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If power lines are physically separated to improve heat characteristics, then heat dissipation is improved, but power integrity and voltage stability deteriorate

Engineering Contradiction:
Improveheat dissipationVSAvoidpower integrity
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent segments the chip into multiple semiconductor regions (first, second, third regions) with different functional purposes. Power lines are selectively connected or disconnected between these regions based on operational modes, allowing heat management and power integrity to be optimized independently in different spatial segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic reconfiguration of power line connections between semiconductor regions. A control circuit dynamically connects or disconnects power lines between regions based on operational requirements, enabling the system to adapt between high-performance mode (power lines connected) and heat-dissipation mode (power lines disconnected).

Inventive Principle:
Principle #15Dynamics

2Temperature

If power lines are spaced apart to manage heat, then thermal performance improves, but voltage supply stability deteriorates

Engineering Contradiction:
Improvethermal performanceVSAvoidvoltage supply stability
Core Design Contradiction:
TemperatureVSStability of the object's composition

Solution Approach 1:

The control circuit dynamically adjusts the connection state of power lines between semiconductor regions based on operational modes. When high voltage stability is required, power lines are connected; when heat dissipation is prioritized, power lines are disconnected, enabling adaptive optimization of both parameters.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the electrical connection parameter (connected/disconnected) of power lines between regions based on operational requirements. This parameter change allows the system to switch between states that optimize for either voltage stability or thermal performance.

Inventive Principle:
Principle #35Parameter changes

3Temperature

If multiple semiconductor regions use separate power lines, then heat characteristics improve, but power delivery stability deteriorates

Engineering Contradiction:
Improveheat characteristicsVSAvoidpower delivery stability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The chip is segmented into multiple independently controllable semiconductor regions. Each region can have its power line connection state independently adjusted, allowing selective thermal management while maintaining power delivery stability in regions that require it.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically reconfigures power line connections between semiconductor regions based on operational modes. The control circuit monitors system state and adjusts connections in real-time, enabling power delivery stability when needed and heat dissipation when needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11830813B2Semiconductor devices including power connection lines
Publication Date: 2023.11.28 SAMSUNG ELECTRONICS CO LTD
  • US11830813B2 patent drawing
  • US11830813B2 patent drawing
  • US11830813B2 patent drawing

AI summary

A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.