Cache Way Prediction Confirmation for Tag-Read Skipping

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Solution Overview

Problem

Cache subsystems consume significant power and experience performance degradation due to repeated verification of cache line predictions, especially in scenarios where the prediction remains correct for subsequent accesses.

Innovation Solution

Implement a confirmation bit mechanism that sets a confirmation indication when a cache line prediction is correct, allowing the cache subsystem to forego tag read and compare operations for subsequent requests, thereby reducing power consumption and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cache subsystem verifies predictions by reading and comparing tags for every cache line access, then the reliability of cache line location prediction is improved, but the power consumption increases significantly

Engineering Contradiction:
Improveprediction verification accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs a preliminary verification of the prediction by reading the address tag from address tag memory and comparing it with the cache tag before fully processing the cache line access. This preliminary action confirms the prediction is correct before committing to the full verification path, thereby reducing unnecessary power consumption while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention extracts only the necessary tag information from the cache structure and uses it for verification purposes. By separating the tag reading operation from the full cache line access, the system can verify predictions using minimal data extraction, reducing the energy required for verification while maintaining accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If the cache subsystem performs complete tag read and compare operations for every cache line, then the measurement precision of cache line location is improved, but the loss of time increases due to redundant operations

Engineering Contradiction:
Improvecache line location accuracyVSAvoidaccess time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs partial verification by reading only the address tag from address tag memory rather than performing complete tag read and compare operations for every cache line access. This partial action is sufficient to confirm the prediction when correct, reducing time loss while maintaining the necessary measurement precision for cache line location.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

When the prediction is confirmed to be correct through the preliminary tag comparison, the system skips the remaining verification operations and proceeds directly to cache line access. This skipping of redundant operations significantly reduces access time while maintaining measurement precision through the initial tag verification.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Productivity

If the cache subsystem sets and stores confirmation bits for correct predictions, then the productivity of repeated cache line accesses is improved, but the device complexity increases

Engineering Contradiction:
Improveaccess speed for repeated requestsVSAvoidconfirmation bit storage structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system creates a simplified copy of the verification state using confirmation bits stored in confirmation bit memory. Instead of maintaining complex verification state throughout the cache structure, the system uses simple bit copies that indicate whether a prediction has been verified, enabling fast access for repeated requests with minimal added complexity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The verification state is segmented into separate confirmation bits stored in dedicated confirmation bit memory, decoupling the complexity of prediction verification from the main cache structure. This segmentation allows the confirmation bits to be independently managed and accessed, improving productivity for repeated accesses while keeping the overall device complexity manageable.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12481591B2Prediction confirmation for cache subsystem
Publication Date: 2025.11.25 APPLE INC
  • US12481591B2 patent drawing
  • US12481591B2 patent drawing
  • US12481591B2 patent drawing

AI summary

A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.