Cache Block Prefetch Messaging for Command Bus Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit systems face inefficiencies in bandwidth utilization due to the need for multiple prefetch commands across different levels of cache, leading to increased consumption on command busses and reduced overall system bandwidth.
Innovation Solution
Implementing a prefetch message that encodes multiple cache block prefetches into a single compressed message, allowing simultaneous access to multiple cache blocks at various levels without adding additional command busses, using a bit field to indicate specific cache blocks within a group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple prefetch commands are used to access cache blocks at different levels, then cache access flexibility is improved, but bandwidth utilization deteriorates due to increased command bus consumption
Solution Approach 1:
The patent combines multiple prefetch commands into a single compressed message that can simultaneously address multiple cache blocks at different cache levels. This merging approach reduces command bus consumption while maintaining the ability to access diverse cache locations, thereby improving bandwidth utilization without sacrificing cache access flexibility.
Solution Approach 2:
The compressed prefetch message structure is designed to be universal, capable of addressing multiple cache blocks across different cache levels (L1, L2, L3) within a single command. This multi-functional message format eliminates the need for separate commands for each cache level, reducing overall command bus traffic while preserving adaptability to various cache access scenarios.
2Productivity
If additional command busses are added to handle multiple prefetches, then prefetching capability is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter structure of prefetch commands by compressing multiple prefetch requests into a single message with encoded address information. Instead of adding more command busses, the solution modifies the command format to include multiple address fields that can be decoded to target different cache blocks, thereby improving prefetching capability without increasing hardware complexity.
Solution Approach 2:
The patent introduces a new dimension to the prefetch command by encoding multiple cache block addresses within a single message structure. This dimensional expansion allows the system to address multiple cache locations without adding physical command busses, effectively improving prefetching capability while maintaining the existing command bus architecture.
3Loss of energy
If compressed prefetch messages are used, then bandwidth utilization is improved, but message encoding complexity increases
Solution Approach 1:
The compressed prefetch message is segmented into distinct fields, with each field representing a specific cache block address. This segmentation allows for systematic encoding and decoding processes, where each address component can be independently manipulated. The structured segmentation reduces the overall encoding complexity compared to creating a completely new compressed format, while still achieving bandwidth optimization.
Data Source
AI summary
Prefetch circuitry may be configured to transmit a message to prefetch one or more cache blocks of a group. The message may indicate an address for the group of cache blocks and a bit field that indicates the one or more cache blocks of the group to prefetch. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.


