Storage Controller Cache Prioritization for Higher Read Hit Ratios

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Solution Overview

Problem

Existing storage devices face challenges in maximizing cache memory utilization due to inefficient management of data retention based on data characteristics, leading to decreased cache hit ratios and overall performance.

Innovation Solution

A storage controller that manages cache memory by setting priorities based on data characteristics, such as reusability, to selectively retain high-priority data and evict low-priority data, thereby optimizing cache memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache memory stores more data to increase cache hit ratio, then operating speed improves, but cache memory management complexity increases

Engineering Contradiction:
Improveoperating speedVSAvoidcache memory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the parameter of data priority assignment by introducing a priority field in cache entries and implementing priority-based replacement policies. This allows the system to manage cache memory more efficiently by dynamically prioritizing data based on access patterns and data characteristics, resolving the contradiction between increasing cache hit ratio and managing cache complexity.

Inventive Principle:
Principle #35Parameter changes

2Speed

If cache memory retains data longer to increase cache hit ratio, then operating speed improves, but cache memory utilization decreases

Engineering Contradiction:
Improveoperating speedVSAvoidcache memory utilization
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent implements dynamic cache management by introducing priority-based eviction policies and dynamic priority assignment. Cache entries are not statically retained but dynamically managed based on priority levels, allowing the system to extend retention for high-priority data while evicting low-priority data to maintain high utilization. This resolves the contradiction between retaining data longer and maintaining high cache utilization.

Inventive Principle:
Principle #15Dynamics

3Reliability

If priority-based data retention is implemented, then cache hit ratio increases, but device complexity increases

Engineering Contradiction:
Improvecache hit ratioVSAvoidcache management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments cache management into priority-based categories by introducing priority fields and classification mechanisms. Data is segmented into different priority levels (e.g., high, medium, low) based on access patterns and characteristics, allowing selective retention and eviction. This segmentation approach increases cache hit ratio while managing complexity through structured priority classification rather than unmanaged complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4432102B1Storage controller and operating method of the storage controller
Publication Date: 2026.02.18 SAMSUNG ELECTRONICS CO LTD
  • EP4432102B1 patent drawingFigure 1
  • EP4432102B1 patent drawingFigure 2
  • EP4432102B1 patent drawingFigure 3

AI summary

A storage controller includes a host interface configured to communicate with a host, a buffer memory configured to buffer data read from a non-volatile memory, a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines, and a cache controller configured to manage a status bitmap. The status bitmap indicates priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap. In this case, the operation corresponding to the request corresponds to one of normal read, prefetch, read-after-read, and read-after-prefetch.