Multi-Core Cache Probe Bypassing Tag Directories for Silent Invalidation
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Solution Overview
Problem
In multi-core processor systems, cache coherence protocols face challenges in handling silent invalidations of shared data copies without notifying record-keeping structures, leading to inefficiencies in data retrieval and increased overhead due to the need to restart requests when a cache line is found to be invalid.
Innovation Solution
The implementation of a One Time Read Prior (OTRprior) command that allows bypassing tag-directories to directly retrieve data from memory, ensuring data service without restarting the request even if the probed core has invalidated the cache line, by determining the last accessor and sending a request for the previously accessed version of the data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cache coherence protocol uses a centralized tag directory to track cache line locations and send probes to the last accessor, then data retrieval can be optimized, but the system fails when the probed core has silently invalidated the cache line without notification
Solution Approach 1:
The patent applies preliminary action by having the requesting core send a backup request to memory simultaneously with the probe to the last accessor. This backup request ensures that if the cache line has been silently invalidated, the requesting core can still retrieve the data from memory without restarting the entire request, thus maintaining protocol robustness while preserving data retrieval efficiency
Solution Approach 2:
The patent implements beforehand cushioning by preparing a fallback mechanism (backup request to memory) in advance of potential cache invalidation issues. This cushioning ensures that the system can handle the adverse event of silent invalidation without failing, thus resolving the contradiction between optimization and robustness
2Reliability
If the protocol restarts the request when a cache line is found invalid, then cache coherence is maintained, but pipeline throughput decreases due to redundant operations
Solution Approach 1:
The patent applies preliminary action by pre-sending a backup request to memory while the probe is in flight. This allows the system to maintain cache coherence through the backup request while avoiding pipeline restarts, thus preserving both reliability and productivity
Solution Approach 2:
The patent implements continuity of useful action by ensuring that the backup request to memory is already in progress before the invalidation is detected. This eliminates the need to restart the request, maintaining continuous useful action in the pipeline and preventing throughput degradation
3Speed
If the system sends probes through the tag directory to find the last accessor, then data can be retrieved from cache, but redundant operations occur when the cache line is silently invalidated
Solution Approach 1:
The patent applies preliminary action by initiating a backup request to memory at the same time as the probe is sent to the last accessor. This preliminary action ensures that even if the probe fails due to silent invalidation, the backup request is already in progress, eliminating redundant operations and time loss
Data Source
AI summary
A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.