Cache Probe Traffic Reduction via Directory-Based Access Tracking
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Solution Overview
Problem
Conventional multi-processor systems experience inefficiencies due to false sharing, leading to increased cache-coherency probe traffic and performance overhead, as they broadcast updates even when not all processors access the shared data objects, necessitating a more effective method to manage cache coherency.
Innovation Solution
Implementing probe-filter logic within the processing units to maintain a directory of cache lines, tracking access by each processor, and only sending probes when necessary, thereby reducing unnecessary probe traffic by determining which processors access specific data objects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cache-coherency protocols broadcast probes to all processors, then cache coherency is maintained, but unnecessary probe traffic increases and performance decreases
Solution Approach 1:
The patent segments the cache line into multiple data objects and tracks access to each individual data object separately. Instead of treating the entire cache line as a single unit, the system divides it into manageable parts (data objects) and monitors which ones are accessed by which processors. This segmentation allows the system to send probes only for specific data objects that are actually accessed, rather than broadcasting to all processors for the entire cache line.
Solution Approach 2:
The patent implements local quality by tracking access patterns at the data object level rather than uniformly across the entire cache line. Each data object maintains its own access tracking mechanism, allowing the system to identify which data objects are locally accessed by which processors. This enables differentiated probe sending behavior based on the specific data object and processor combination, reducing unnecessary probes while maintaining coherency where needed.
2Productivity
If padding data is used to prevent false sharing, then false sharing is reduced, but memory footprint increases and performance deteriorates
Solution Approach 1:
The patent performs preliminary tracking of access patterns for each data object within cache lines before false sharing problems arise. By maintaining access information in advance and monitoring which processors access which data objects, the system can proactively determine when probes are necessary. This preliminary action eliminates the need for padding data to prevent false sharing, as the system can intelligently manage cache coherency based on actual access patterns rather than relying on conservative padding strategies.
Data Source
AI summary
Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node.