Cache Probe Transaction Filtering for Multiprocessor Systems
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Solution Overview
Problem
Multiprocessor systems with multiple cache devices face inefficiencies in providing the latest data due to high rates of wasted cache coherency protocol probes, especially when accelerators and cores access different data sets with low overlap, leading to unnecessary traffic and energy consumption.
Innovation Solution
Implementing scrubber and watcher circuitries to selectively disable cache snoop operations by flushing data from cache devices and monitoring for acknowledgement, thereby reducing unnecessary snoop requests and optimizing cache coherency protocol usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CHA performs cache coherency protocol probes for all memory accesses, then cache coherency is maintained, but unnecessary traffic and energy consumption increase when accelerators access data not cached by cores
Solution Approach 1:
The system performs preliminary actions by having cores issue probe transactions to the CHA before accelerator access. The CHA responds with cache state information (hit/miss indicators) in advance, allowing the accelerator to determine whether subsequent access requires full coherency protocol or can proceed directly to memory access, thus avoiding unnecessary energy consumption while maintaining coherency when needed
Solution Approach 2:
The CHA acts as an intermediary between cores and accelerators, providing cache state information about memory regions. This intermediary mechanism allows accelerators to make informed decisions about memory access without directly invoking full coherency protocols, reducing traffic and energy consumption while preserving cache coherency where applicable
2Reliability
If the CHA services all probe transactions from accelerators, then cache coherency protocol compliance is maintained, but traffic volume increases significantly when accelerators access large data sets with low overlap with core memory access
Solution Approach 1:
The system performs preliminary probe transactions and cache state inquiries before actual accelerator data access. The CHA provides advance information about which memory regions are cached by cores, allowing the accelerator to bypass the CHA for uncached regions and only engage the coherency protocol for cached regions, significantly reducing traffic volume while maintaining protocol compliance
Solution Approach 2:
The memory address space is effectively segmented into cached regions and uncached regions based on CHA probe responses. The accelerator divides its access pattern accordingly, routing accesses to cached regions through the CHA for coherency checking and accesses to uncached regions directly to memory, reducing overall traffic volume while maintaining protocol compliance where needed
Data Source
AI summary
Examples described herein relate to circuitry to selectively disable cache snoop operations issued by a particular processor or its cache manager based on data in a memory address range, to be accessed by the particular processor, having been flushed from one or more other cache devices accessible to other processors. At or after completion of flushing or scrubbing data in the memory address range to memory, the particular processor or its cache manager do not issue snoop operations for accesses to the memory address range. In response to an access by some other device to the memory address range, the processor or cache manager may resume issuing snoop operations.