Cache Program Execute Technique for ECC NAND Flash Memory
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Solution Overview
Problem
NAND flash memory devices face inefficiencies in programming performance due to time-intensive page programming operations, which hinder fast read and program capabilities, especially when internal ECC is enabled and bad block management is required.
Innovation Solution
Implementing a cache program execute technique that utilizes a cache register and a data register to perform error correction coding in parallel with page programming, allowing for overlapping operations and efficient resource utilization during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential programming operations are used with ECC processing, then programming accuracy is maintained, but programming speed deteriorates due to time-intensive page programming operations
Solution Approach 1:
The patent loads multiple pages of program data into the data buffer in advance before the actual programming operation begins. This preliminary loading allows the programming engine to process pages sequentially while data is already prepared, eliminating waiting time and enabling continuous programming operations without interruption.
Solution Approach 2:
The patent implements a continuous programming pipeline where the programming engine processes one page while the data buffer simultaneously loads the next page. This overlapping of operations ensures that the programming engine is never idle, maintaining continuous useful action and maximizing programming throughput.
2Reliability
If ECC processing is performed on each page before programming, then data integrity is ensured, but overall programming throughput deteriorates due to sequential processing requirements
Solution Approach 1:
The patent divides the programming task into independent page segments that can be processed individually by the programming engine. Each page is loaded into the data buffer, programmed, and verified independently, allowing the system to maintain data integrity for each page while enabling parallel preparation of subsequent pages to improve overall throughput.
Solution Approach 2:
The patent introduces a data buffer as an intermediary structure between the host interface and the programming engine. This buffer decouples the data loading process from the programming process, allowing data to be prepared in advance while the programming engine works on previous data, thereby eliminating bottlenecks and improving throughput without compromising data integrity.
3Quantity of substance
If the data buffer is used for loading program data, then data storage capacity is sufficient, but the buffer becomes a bottleneck when programming operations are time-intensive
Solution Approach 1:
The patent utilizes the data buffer to store multiple pages of program data in advance before programming begins. By pre-loading data into the buffer's available capacity, the system prepares sufficient data to keep the programming engine continuously occupied, transforming the buffer from a potential bottleneck into a productivity-enhancing resource.
Solution Approach 2:
The patent extends the data buffer's functionality beyond simple data storage by implementing a multi-page buffer structure that can hold and manage multiple pages simultaneously. This dimensional expansion of buffer usage allows parallel preparation of multiple pages, converting the buffer into a throughput-enhancing component rather than a sequential bottleneck.
Data Source
AI summary
The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.