Cache Memory Random Access for Side-Channel Attack Prevention
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Solution Overview
Problem
Computing systems implementing cryptographic methods are vulnerable to side-channel attacks, particularly power consumption attacks, which exploit measurable physical characteristics like power consumption to derive secret information.
Innovation Solution
A mechanism is introduced to generate a random power profile by enabling a built-in self-test (BIST) module to perform random memory accesses, obscuring power consumption patterns, and using a random timeslot generator to further obfuscate power usage, thereby preventing attackers from deriving sensitive information from power consumption data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic operations are performed using standard cache memory access patterns, then processing efficiency is maintained, but power consumption patterns become predictable and vulnerable to side-channel attacks
Solution Approach 1:
The cache memory is divided into multiple segments or portions, each accessible under different conditions. The patent implements a mechanism where the cache is segmented into portions that can be selectively accessed based on the operation type, allowing secure operations to use randomized access patterns while non-secure operations use standard patterns.
Solution Approach 2:
The cache access pattern is made dynamic by introducing randomization. The patent employs a random access generator that dynamically selects which cache portions to access and in what order, changing the access pattern based on random factors rather than following a fixed or predictable sequence.
2Reliability
If random access patterns are implemented in cache memory to obscure power consumption, then resistance to side-channel attacks improves, but access time and processing speed increase
Solution Approach 1:
The patent applies randomization only to specific portions of cache memory rather than the entire cache. By selectively randomizing access patterns in only certain cache segments during secure operations, the system achieves security benefits while minimizing the impact on overall access performance.
Solution Approach 2:
The random access pattern is implemented periodically or in controlled intervals rather than continuously. The system switches between standardized access patterns and randomized access patterns based on the operation type, applying randomization only when needed for security-critical operations.
3Reliability
If a portion of cache memory is dedicated to random access operations, then power consumption profiling is obscured, but available cache capacity for normal operations decreases
Solution Approach 1:
The cache memory portions are designed to serve multiple functions. The same cache segments that store data for normal operations are also used for randomized access operations during secure cryptographic processing, eliminating the need for separate dedicated memory regions.
Solution Approach 2:
Cache portions used for randomized access during secure operations are temporarily allocated for that purpose and then recovered for normal use afterward. The system dynamically allocates and deallocates cache portions based on operational requirements, ensuring that memory resources are efficiently utilized.
Data Source
AI summary
A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.