Cache Read Control Logic Overlapping Discharge and Moving Operations
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Solution Overview
Problem
Current memory devices face inefficiencies in cache read operations due to non-overlapping execution of discharge and moving operations, leading to increased time requirements for consecutive cache read operations.
Innovation Solution
A memory device with a control logic system that allows partial or complete overlap of discharge and moving operations during cache read commands, optimizing the execution sections to minimize overall operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discharge operation and moving operation are executed sequentially without overlap, then each operation can be completed reliably, but the total time for cache read operations increases
Solution Approach 1:
The discharge operation is initiated in advance before the moving operation completes. The control logic starts discharging the word line while the data is still being transferred from the first latch to the second latch, preparing the system for the next cache read operation without waiting for the current moving operation to fully complete.
Solution Approach 2:
The discharge operation and moving operation are executed in an overlapping manner, allowing both operations to proceed simultaneously rather than sequentially. This continuous execution of useful actions reduces idle time and improves the overall efficiency of cache read operations.
2Loss of time
If discharge operation and moving operation are executed in overlapping manner, then cache read operation time is reduced, but operation complexity increases
Solution Approach 1:
The control logic dynamically adjusts the timing and coordination of the discharge operation and moving operation based on the input cache read commands. The system can flexibly overlap these operations to different extents depending on the specific operational context, optimizing performance without requiring a completely rigid complex control structure.
Data Source
AI summary
A memory device comprises: a page buffer including a first and second latch, a control circuit configured to perform reading data of a word line and storing the data in the first latch, perform discharging the word line, perform moving the data of the first latch to the second latch, and perform outputting the data of the second latch to an exterior, and a control logic configured to control the control circuit such that an execution section of the discharge and moving for a first word line at least partially overlap each other when a second or third cache read command is inputted in a section in which the storage or discharge for the first word line is performed in response to a first cache read command for the first word line.