Caching Frequent Read Disturb Aggressors in Memory
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Solution Overview
Problem
Existing memory subsystems face reliability degradation due to read disturb errors, where frequent read operations on one portion of memory (aggressors) impact neighboring cells (victims), leading to errors and unnecessary data integrity scans, compromising system quality and service.
Innovation Solution
Implementing a probabilistic data integrity scheme that identifies and caches frequent read disturb aggressors, allowing subsequent read operations to be serviced from a cache, thereby reducing the impact on victims and increasing the memory's tolerance to read disturb errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed frequently on one portion of memory (aggressors), then data access speed is improved, but read disturb errors increase impacting neighboring cells (victims)
Solution Approach 1:
A cache is introduced as an intermediary component between the memory subsystem and the read operations. The cache stores copies of data from aggressor locations, allowing frequent reads to be serviced from the cache rather than directly from memory, thereby preventing read disturb errors while maintaining fast access speeds.
Solution Approach 2:
Data from aggressor memory locations is copied to a cache structure. This copying mechanism allows the system to serve read requests from the cache copy rather than repeatedly accessing the original memory location, eliminating read disturb effects on victim cells while preserving data access performance.
2Reliability
If data integrity scans are performed to detect read disturb errors, then data reliability is improved, but system productivity decreases due to unnecessary scans
Solution Approach 1:
The system performs preliminary action by proactively caching data from potential aggressor locations before read disturb errors can occur. This preventive caching eliminates the need for subsequent data integrity scans to detect errors, maintaining reliability while avoiding the productivity loss associated with frequent scanning operations.
Solution Approach 2:
The system implements feedback by monitoring read operation patterns to identify aggressor locations. When a location is identified as an aggressor, the system responds by caching its data, creating a feedback loop that prevents error generation and eliminates the need for continuous integrity scanning.
3Reliability
If read disturb mitigation techniques are implemented, then memory reliability is improved, but device complexity increases
Solution Approach 1:
A cache is introduced as an intermediary component between the memory subsystem and the read operations. The cache stores copies of data from aggressor locations, allowing frequent reads to be serviced from the cache rather than directly from memory, thereby preventing read disturb errors while maintaining fast access speeds.
Solution Approach 2:
Data from aggressor memory locations is copied to a cache structure. This copying mechanism allows the system to serve read requests from the cache copy rather than repeatedly accessing the original memory location, eliminating read disturb effects on victim cells while preserving data access performance.
Data Source
AI summary
Exemplary methods, apparatuses, and systems include receiving a read operation directed to an aggressor location. An integrity scan of a victim location of the aggressor location is performed to determine an error value for the victim location. Data from the aggressor location is copied to a cache in response to determining the error value for the victim location satisfies a first error value threshold. The cache is a different type of memory from the aggressor location.