Processor Cache Redirection Across Sets to Reduce Cache Misses
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Solution Overview
Problem
Existing cache systems face inefficiencies due to cache misses and thrashing, particularly when cache lines are full and memory blocks need to be evicted, leading to reduced performance and increased power consumption.
Innovation Solution
Implementing a cache system that supports redirection of memory blocks between cache lines, allowing storage in different sets when the default set is full, with metadata tracking the redirection for efficient retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the cache uses traditional set-associative mapping where memory blocks are stored only in their default set, then the cache structure is simple and easy to manage, but cache misses increase when the default set is full and memory blocks need to be evicted
Solution Approach 1:
The patent segments the cache lookup process into two independent phases: first checking the default set, then checking the redirected set if needed. This segmentation allows the cache to maintain simple default mapping while adding redirection capability without significantly increasing overall complexity.
Solution Approach 2:
The patent introduces redirection metadata as an intermediary mechanism that stores mapping information between default sets and actual storage locations. This intermediary allows memory blocks to be redirected to alternative sets without requiring complex dynamic reconfiguration of the cache structure.
2Productivity
If the cache allows memory blocks to be redirected to non-default sets, then cache utilization improves and cache misses reduce, but the metadata management becomes more complex
Solution Approach 1:
The metadata is segmented into two distinct components: redirection metadata stored in the default set and presence metadata stored in the redirected set. This segmentation distributes the management burden across different cache locations and simplifies the overall metadata structure.
Solution Approach 2:
The cache system uses self-service mechanisms where the redirection metadata automatically indicates whether a memory block has been redirected, and the presence metadata in the redirected set automatically indicates whether the block is currently stored there. This eliminates the need for complex centralized management.
3Speed
If the cache checks only the default set for memory block presence, then the lookup process is fast and simple, but cache misses occur when blocks have been redirected to other sets
Solution Approach 1:
The patent performs preliminary checking of the default set first, which contains the redirection metadata. Only if the block is not found in the default set does the system proceed to check the redirected set. This preliminary action maintains fast lookup for the common case while providing a fallback path for redirected blocks.
Solution Approach 2:
The patent adds another dimension to the cache lookup process by introducing a second lookup path through the redirected set. This dimensional expansion allows the system to search both the default set and the redirected set, increasing the probability of finding cached blocks without significantly impacting the speed of the primary lookup path.
Data Source
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AI summary
Various example embodiments of a processor cache are presented herein. The processor cache may be configured to support redirection of memory blocks between cache lines, including between cache lines in different sets of the processor cache, thereby improving the efficiency of the processor cache by increasing the utilization of the processor cache and reducing cache misses for the processor cache. The redirection of memory blocks between cache lines may include redirection of a memory block from being stored in a first cache line of a first set of the processor cache which is the default set for the memory block (e.g., when the first set does not have any empty cache lines) to a second cache line of a second set of the processor cache which is not the default set for the memory block (e.g., the second set may be any set having at least one empty cache line).