Cache Memory Reference Count Inhibits Premature Data Replacement
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Solution Overview
Problem
Existing cache memory systems face excessive data replacement issues due to premature release of lock bits, leading to replacement of prefetched data that has not been used multiple times, which affects processor performance by increasing memory latency.
Innovation Solution
A data processing apparatus with a cache memory unit that includes a data array structure with reference counts for each entry, where the prefetch unit inhibits replacement until the reference count reaches zero, ensuring that prefetched data is not replaced until it is used by the fetch operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If prefetch is performed excessively early, then memory latency can be hidden, but prefetched data may be replaced with subsequently prefetched data
Solution Approach 1:
The patent applies preliminary action by performing prefetch operations in advance before the processor actually needs the data. The prefetch unit proactively loads data from main memory to cache memory ahead of time, allowing the processor to access already-prefetched data without experiencing memory latency. This is achieved through the fetch unit that independently initiates prefetch operations based on predicted future data needs.
Solution Approach 2:
The patent implements feedback through the reference count mechanism that tracks how many times prefetched data has been accessed by the processor. When data is prefetched, a reference count is initialized. Each time the processor accesses the data, the reference count is decremented. When the reference count reaches zero, the data becomes eligible for replacement. This feedback loop ensures that data which is frequently accessed retains its cache position, while data that is not accessed can be safely replaced.
2Reliability
If lock bit is set to prevent replacement of prefetched data, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by using a reference count parameter instead of a simple binary lock bit. The reference count provides a graduated mechanism where data can be retained based on its access frequency rather than a simple locked/unlocked state. This parameter-based approach replaces the complex lock bit mechanism with a more flexible counting system that automatically manages data retention based on actual usage patterns.
Solution Approach 2:
The patent implements self-service through the automatic reference count decrementing mechanism. Each time the processor accesses prefetched data, the reference count is automatically decremented without requiring external control logic. The cache replacement policy automatically uses this reference count information to determine which data to replace, eliminating the need for complex external control structures and lock bit management.
3Reliability
If reference count mechanism is implemented, then excessive data replacement is suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the cache memory into multiple entries, each with its own independent reference count. This allows each cached data item to be managed independently based on its own access pattern. The segmentation of the cache into ways and sets enables parallel management of multiple reference counts, distributing the complexity across many simple independent counters rather than requiring complex centralized control logic.
Data Source
AI summary
A cache memory device includes a data array structure including a plurality of entries identified by indices and including, for each entry, data acquired by a fetch operation or prefetch operation and a reference count associated with the data. The reference count holds a value obtained by subtracting a count at which the entry has been referred to by the fetch operation, from a count at which the entry has been referred to by the prefetch operation. As for an entry created by the prefetch operation, a prefetch device inhibits replacement of the entry until the value of the reference count of the entry becomes 0.