Cache Refetch Circuitry for Coherency Latency Reduction
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Solution Overview
Problem
In coherent cache systems, the write invalidate mechanism can lead to data being removed from a master device's local cache before it is finished being used, causing latency and impacting performance, as the consumer's cache miss occurs when the producer evicts the data from its cache before the consumer requests it.
Innovation Solution
Implementing refetch control circuitry that automatically initiates a refetch of invalidated data values into the cache when a coherency action results in invalidation, triggered by the cache coherency circuitry, to ensure data availability and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write invalidate mechanism is used to maintain cache coherency, then cache coherency is ensured and power consumption is reduced by avoiding memory accesses, but data may be removed from a master device's local cache before it is finished being used, causing latency and impacting performance
Solution Approach 1:
The patent applies preliminary action by having the consumer master device proactively request invalidated data from the producer master device's cache before the data is completely evicted. The refetch control circuitry detects invalidation events and automatically triggers refetch operations to retrieve needed data, ensuring it remains available in the consumer's cache without waiting for natural eviction or subsequent memory requests. This resolves the contradiction by maintaining cache coherency through invalidate mechanisms while preventing performance degradation through proactive data recovery.
2Ease of manufacture
If the write invalidate mechanism is used, then the coherency protocol is simple to implement, but the consumer master device may experience cache misses when needing data that was invalidated
Solution Approach 1:
The patent applies self-service by enabling the consumer master device to automatically detect and recover invalidated data through a refetch control circuitry that monitors invalidation events and autonomously triggers refetch operations. The system serves itself by detecting when data is invalidated and automatically initiating the retrieval process without requiring manual intervention or complex external management. This maintains the simplicity of the write invalidate protocol while adding intelligent self-recovery capability that prevents cache misses and maintains high data access speed.
3Quantity of substance
If data is evicted from cache to make space for new data, then cache capacity is maintained, but the evicted data may still be needed by the master device or other master devices
Solution Approach 1:
The patent applies feedback by implementing a mechanism where the refetch control circuitry monitors invalidation events and uses this feedback information to determine when refetch operations are needed. When data is invalidated due to eviction, the system receives feedback about the data's new status and automatically initiates refetch operations to restore availability. This feedback-driven approach allows the cache to maintain full capacity while ensuring data reliability through automatic recovery of evicted data that is still needed by master devices.
Data Source
AI summary
A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.