Cache Region Allocation Reducing Remainder Calculation Load
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Solution Overview
Problem
Existing cache management methods face high processing loads when reducing the number of allocated divided regions, particularly due to the need for remainder calculations for each data block to determine storage destinations, which increases calculation load and time.
Innovation Solution
The information processing apparatus allocates and reduces divided regions in a processor-controlled cache by identifying target regions based on positional relationships before and after reduction, allowing data blocks to be stored in ascending order of purging priority, thereby reducing the number of calculations required for determining storage destinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of allocated divided regions is reduced by conventional methods, then cache memory can be reallocated to other processes, but the processing load and time for determining storage destinations increases due to remainder calculations for each data block
Solution Approach 1:
The cache is divided into multiple divided regions that can be independently allocated to different processes. When reducing the number of allocated divided regions, the patent segments the data blocks into groups based on their address ranges, allowing selective migration of data blocks to remaining divided regions without requiring remainder calculations for each individual data block.
Solution Approach 2:
The patent performs preliminary identification of data blocks that need to be migrated before the actual migration process. By pre-determining which data blocks should be moved based on address range mapping, the system prepares the migration plan in advance, avoiding complex real-time calculations during the cache reallocation process.
2Measurement precision
If remainder calculations are performed for each data block to determine storage destination, then accurate storage destination determination is achieved, but the calculation time and processing load increases significantly
Solution Approach 1:
The patent extracts the calculation burden from individual data block level to the divided region level. Instead of performing remainder calculations for each data block, the system performs calculations at the divided region level to identify target regions, then migrates data blocks in batches based on address range mapping, significantly reducing the number of calculations required.
Solution Approach 2:
The patent uses address range mapping tables that pre-store the correspondence between source and target divided regions. This mapping table acts as a copy of the allocation structure, allowing the system to determine storage destinations by table lookup rather than performing complex remainder calculations for each data block.
Data Source
AI summary
An information processing apparatus includes a processor. The processor configured to allocate, to a process, a first number of first divided regions from among a plurality of divided regions obtained by division of a cache, and determine, based on an address of each data block corresponding to the process and the first number, a storage destination of the data block corresponding to the process from among the first divided regions. The processor configured to determine a second number that is a divisor of the first number, identify, for the individual first divided regions after the reduction, second divided regions from among the first divided regions before the reduction, determine data blocks to be stored in the individual first divided regions after the reduction by allocating data blocks to the first divided regions after the reduction from the corresponding second divided regions in ascending order of purging order.