Data Cache Region Prefetcher for Non-Sequential Access Patterns

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing cache systems in processing devices face challenges in efficiently predicting and prefetching data lines based on complex access patterns, leading to increased latency and reduced performance.

Innovation Solution

A data cache region prefetcher is introduced, which recognizes cache access patterns by creating regions around data cache misses and uses these patterns to issue prefetch requests, thereby anticipating future data accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional cache systems are used without region-based prefetching, then device complexity is lower, but latency increases and performance decreases

Engineering Contradiction:
ImprovelatencyVSAvoidcache system complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The cache system is segmented into multiple regions, each tracked independently in the region history table. This segmentation allows the prefetcher to identify and exploit access patterns within specific regions without requiring complex global analysis, thereby reducing latency while maintaining manageable system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by proactively prefetching data into the cache before it is actually requested by the processor. The region prefetcher monitors access patterns and issues prefetch requests in advance, eliminating wait time for future data accesses and reducing overall latency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If region-based prefetching is implemented, then cache hit rates improve, but device complexity increases

Engineering Contradiction:
Improvecache hit rateVSAvoidprefetcher structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A region history table is introduced as an intermediary data structure between the cache and the prefetcher logic. This table stores region tags and access pattern information, serving as a mediator that simplifies the prefetcher's decision-making process. Instead of complex real-time analysis, the prefetcher consults this intermediary table to determine which regions to prefetch, thereby improving cache hit rates while keeping the prefetcher structure relatively simple.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If multiple streams are tracked independently, then prefetching accuracy improves, but device complexity increases

Engineering Contradiction:
Improveaccess pattern prediction accuracyVSAvoidstream tracking mechanism
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The prefetcher divides the memory address space into multiple independent regions, each with its own access pattern history. By segmenting the tracking mechanism into region-specific entries in the region history table, the system can accurately predict access patterns for each region independently without requiring a monolithic complex tracking structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each region in the region history table maintains its own local access pattern information and prefetching parameters. This local quality approach allows the system to optimize prefetching accuracy for each specific region based on its unique access characteristics, rather than applying a single global strategy, thereby improving overall prediction accuracy while keeping each local tracker relatively simple.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12204459B2Data cache region prefetcher
Publication Date: 2025.01.21 ADVANCED MICRO DEVICES INC
  • US12204459B2 patent drawing
  • US12204459B2 patent drawing
  • US12204459B2 patent drawing

AI summary

A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.