Memory Subsystem Cache Register Release for Overlapped Programming

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Solution Overview

Problem

Existing memory programming algorithms result in prolonged programming times due to the cache register being released only after the completion of all programming loops and voltage discharge phases, preventing new data from being loaded until the previous operation is finalized, leading to inefficiencies and potential data recovery issues.

Innovation Solution

Implementing an advanced cache register release mechanism based on a prediction condition, allowing the cache register to be released early during the programming process, enabling parallel execution of subsequent operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cache register is released only after completion of all programming loops and voltage discharge phases, then data reliability is maintained, but programming time is prolonged

Engineering Contradiction:

Improvedata reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by releasing the cache register before the voltage discharge phase completes. The cache register is released after programming loops finish but before voltage discharge, allowing the next programming operation to start in advance. This resolves the contradiction by maintaining data reliability (through proper sequencing) while reducing programming time (by overlapping operations).

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by enabling overlapping of programming operations. The cache register release allows the bus to remain busy and productive by initiating the next programming operation while the current one is still in voltage discharge phase. This eliminates idle waiting time and maintains continuous useful action throughout the programming process.

Inventive Principle:

Principle #20Continuity of useful action

2Loss of time

If the cache register is released early during programming, then programming time is reduced, but data recovery issues may occur

Engineering Contradiction:

Improveprogramming timeVSAvoiddata recovery

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent uses preliminary action strategically by releasing the cache register at the optimal moment - after programming loops complete but before voltage discharge finishes. This timing ensures that data is properly programmed and stable before release, preventing data recovery issues while still enabling time savings through early release and overlapping operations.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If the cache register is held busy until programming completion, then data integrity is ensured, but bus efficiency is reduced

Engineering Contradiction:

Improvedata integrityVSAvoidbus efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies continuity of useful action to improve bus efficiency by releasing the cache register early, allowing the bus to remain busy with productive operations. The cache register is released after programming loops but before voltage discharge, enabling the next programming operation to start immediately. This eliminates bus idle time while maintaining data integrity through proper sequencing and timing.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12431197B2Programming operation using cache register release in a memory sub-system

Publication Date: 2025.09.30 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device initiates a programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. During execution of the programming operation, a programming status associated with the set of memory cells. In response to determining the programming status satisfies a condition, causing a release of a set of data associated with the programming operation from a cache register.