Cache Replacement Scheme Reducing Transaction Rollbacks

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Solution Overview

Problem

Transaction rollbacks in microprocessors result in performance penalties due to the need to restore a consistent state after errors, particularly affecting large or long-running transactions.

Innovation Solution

Implementing a multi-level cache replacement scheme that prioritizes cachelines based on their likelihood of causing transaction rollbacks, using a tree-LRU replacement scheme to select cachelines with higher replacement priority levels for replacement, thereby reducing the likelihood of transaction rollbacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transaction processing is implemented to ensure data integrity, then reliability is improved, but productivity deteriorates due to performance penalties from rollbacks

Engineering Contradiction:

Improvedata integrityVSAvoidprocessing performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by proactively identifying and evicting cachelines that are most likely to cause transaction rollbacks before transactions occur. The system uses replacement priority levels to pre-determine which cachelines should be removed first, preventing potential conflicts rather than reacting to them after they cause rollbacks. This reduces the frequency and impact of rollbacks, thereby improving processing performance while maintaining data integrity.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If standard LRU cache replacement is used, then device complexity is kept simple, but reliability deteriorates due to higher transaction rollback likelihood

Engineering Contradiction:

Improvecache control complexityVSAvoidtransaction completion success

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by assigning different replacement priority levels to different cachelines based on their specific characteristics and likelihood of causing rollbacks. Instead of treating all cachelines uniformly as in standard LRU, the system makes localized differentiation where cachelines with higher rollback potential receive lower priority levels and are evicted first. This targeted approach improves transaction reliability without requiring complete redesign of the cache control mechanism.

Inventive Principle:

Principle #3Local quality

3Productivity

If cacheline replacement prioritizes preventing rollbacks, then productivity is improved, but device complexity increases due to multi-level replacement scheme

Engineering Contradiction:

Improveprocessing performanceVSAvoidcache replacement mechanism

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the cache replacement decision process into multiple levels based on replacement priority levels. The system segments cachelines into different groups (e.g., high priority, medium priority, low priority) based on their rollback likelihood, and applies different replacement strategies to each segment. This structured segmentation makes the complex replacement policy more manageable and implementable while achieving improved productivity through reduced rollbacks.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10019381B2Cache control to reduce transaction roll back

Publication Date: 2018.07.10 NVIDIA CORP

AI summary

In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.