Two-Tier Cache Retention Management via Application Hints

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current cache management mechanisms in storage systems with a two-tiered cache configuration, comprising DRAM and SCM, face challenges in efficiently managing data retention times, leading to suboptimal performance due to limited write endurance and access speed differences between the two memory types.

Innovation Solution

Implementing a method that receives minimum and maximum retention time indications from host applications for tracks in the cache, using these hints to manage track placement and demotion in both DRAM and SCM caches, with DRAM as the higher tier and SCM as the lower tier, and employing LRU lists with multiple insertion points to optimize data retention based on access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is retained in DRAM cache for longer periods, then cache hit rate improves, but write endurance of DRAM is wasted and SCM write opportunities are lost

Engineering Contradiction:

Improvecache hit rateVSAvoidwrite endurance consumption

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The cache management system dynamically adjusts retention policies based on application-provided hints. Tracks with minimum retention time hints are kept in DRAM for at least that duration, while tracks with maximum retention time hints are demoted to SCM after that duration. This dynamic adjustment optimizes cache hit rate while preventing unnecessary consumption of DRAM write endurance.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the retention parameter for different tracks based on application hints. By setting minimum and maximum retention times as parameters, the system can control how long each track remains in DRAM, balancing cache performance with write endurance conservation.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If data is demoted from DRAM to SCM earlier, then DRAM write endurance is preserved, but cache miss rate increases

Engineering Contradiction:

Improvewrite endurance efficiencyVSAvoidcache miss rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system performs preliminary actions by demoting tracks to SCM at their maximum retention time before they would naturally be evicted. This preliminary demotion prepares the cache for future writes by moving data to SCM in advance, preserving DRAM write endurance while maintaining optimal cache performance through timely data placement.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses application-provided minimum and maximum retention time hints as feedback to control demotion timing. This feedback mechanism ensures that tracks are demoted at optimal moments, balancing write endurance efficiency with cache hit rate maintenance.

Inventive Principle:

Principle #23Feedback

3Quantity of substance

If SCM is used as lower tier cache, then storage capacity is increased, but access speed decreases compared to DRAM

Engineering Contradiction:

Improvecache storage capacityVSAvoiddata access speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The cache is segmented into two tiers: DRAM for frequently accessed data requiring high speed, and SCM for less frequently accessed data where capacity is more important than speed. This segmentation allows the system to leverage the high speed of DRAM for critical data while using the large capacity of SCM for bulk storage, optimizing overall performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

SCM acts as an intermediary between DRAM and permanent storage. It provides a large-capacity buffer that can hold data waiting to be written to permanent storage or data that has been read from permanent storage but is not yet needed in DRAM. This intermediary role resolves the speed-capacity tradeoff by providing a transition zone with intermediate characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Ease of manufacture

If LRU policy is used for cache replacement, then implementation simplicity is maintained, but application-specific retention requirements are not met

Engineering Contradiction:

Improvecache management simplicityVSAvoidapplication-specific retention handling

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The cache management system maintains universal LRU tracking for all tracks while adding multi-functionality through application-specific retention handling. The system universally tracks usage patterns but can also honor application-provided minimum and maximum retention time hints, making it adaptable to different application requirements without sacrificing implementation simplicity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11210237B2Integration of application indicated minimum and maximum time to cache for a two-tiered cache management mechanism

Publication Date: 2021.12.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.