Processor Cache Retention Region for Powered-Down State Coherence
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Solution Overview
Problem
Conventional processing systems fail to maintain cache coherence between powered-up caches and caches that are powered down, leading to performance degradation when processor cores exit a powered-down state due to the absence of up-to-date information in the caches.
Innovation Solution
The solution involves storing entries in a cache, such as a translation lookaside buffer (TLB) or a lower-level cache, in a retention region that receives a retention voltage while the processor core is in a powered-down state. This retention region can be implemented in a higher-level cache, external memory, or within the cache itself, allowing for the restoration of cache entries and invalidation information when the processor core powers up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If caches are flushed and powered-down prior to placing processor cores in powered-down state, then leakage current is reduced, but cache coherence is lost and performance degrades when exiting powered-down state
Solution Approach 1:
The cache system is segmented into two distinct regions: a retention region that maintains power and cache coherence during powered-down state, and a non-retention region that is flushed and powered-down for leakage reduction. This segmentation allows simultaneous achievement of low power consumption and cache coherence maintenance.
Solution Approach 2:
Different regions of the cache are assigned different functional qualities: the retention region maintains active cache entries with power supplied, while the non-retention region is flushed and powered-down. This local differentiation enables selective preservation of cache coherence only where necessary.
2Loss of energy
If cache entries are flushed to higher-level cache or external memory before powering down, then leakage current is reduced, but access time increases when processor core exits powered-down state
Solution Approach 1:
The retention region is pre-configured to hold cache entries in a ready state before the processor core exits powered-down mode. This preliminary preparation eliminates the need for time-consuming cache refilling operations, reducing access time upon wake-up.
Solution Approach 2:
The retention region acts as an intermediary structure that bridges the powered-down state and the active state. It temporarily holds cache entries during the powered-down period, serving as a buffer that enables fast recovery without requiring full cache refill from higher-level caches or external memory.
3Reliability
If retention voltage is supplied to retention region during powered-down state, then cache coherence is maintained, but power consumption increases
Solution Approach 1:
The cache power distribution is segmented into two pathways: retention voltage supplied only to the retention region to maintain cache coherence, and power removed from the non-retention region to reduce leakage. This selective power distribution achieves reliability where needed while minimizing overall power consumption.
Solution Approach 2:
Power supply quality is differentiated locally across the cache structure: the retention region receives continuous retention voltage to maintain operational state and cache coherence, while the non-retention region operates in a powered-down state with minimal leakage. This local quality differentiation optimizes the balance between reliability and energy consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accelerates the performance of processor cores when they exit a powered-down state by maintaining cache coherence and ensuring that up-to-date information is readily available, thereby reducing the overhead associated with reinitializing cache entries.
Implementation Method 1
storing entries in a cache, such as a translation lookaside buffer (TLB) or a lower-level cache, in a retention region that receives a retention voltage while the processor core is in a powered-down state
Data Source
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AI summary
A processor core (215) associated with a first cache (205) initiates entry into a powered-down state. In response, information representing a set of entries (220) of the first cache are stored in a retention region (230) that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.