Memory-Side Cache Rinsing for DRAM Bandwidth Efficiency
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Solution Overview
Problem
The presence of a memory-side cache in computing systems interferes with the efficient ordering of DRAM transactions due to cache hits and misses, leading to suboptimal bandwidth utilization and increased latency, especially during phases of high cache hit rates where main memory bandwidth remains underutilized.
Innovation Solution
Implementing a memory-side cache that performs read and write 'rinsing' of cached data when spare DRAM bandwidth is available, preserving the original transaction order and reducing the number of memory transactions by writing through the cache whether it results in a cache hit or miss, thus maintaining optimal DRAM efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory-side cache is used to improve memory access speed, then memory access latency is reduced, but the ordering of DRAM transactions becomes inefficient and bandwidth utilization decreases
Solution Approach 1:
The patent performs cache rinsing in advance during periods of spare bandwidth, proactively clearing dirty data from the cache before it can interfere with future transaction ordering. This preliminary action prevents the cache from becoming a source of transaction reordering conflicts, thus maintaining both fast access and efficient bandwidth utilization.
Solution Approach 2:
The patent continuously monitors DRAM bandwidth availability and performs cache rinsing operations during idle periods, ensuring that the cache remains clean and ready to maintain efficient transaction ordering when bandwidth is needed. This continuous monitoring and adaptive rinsing maintains optimal performance without interrupting normal cache operations.
2Productivity
If cache rinsing is performed to maintain transaction ordering, then DRAM efficiency is improved, but additional memory transactions are generated increasing overhead
Solution Approach 1:
The patent performs partial rinsing by selectively targeting only the dirty cache lines that need to be cleared, rather than flushing the entire cache. This partial action is sufficient to maintain transaction ordering efficiency while minimizing the number of rinsing transactions required, thus reducing overhead.
Solution Approach 2:
The cache controller autonomously manages the rinsing process by monitoring its own dirty state and initiating rinsing operations only when necessary. This self-service approach eliminates the need for external intervention and ensures rinsing occurs at optimal moments without adding unnecessary overhead from external control mechanisms.
3Reliability
If write-through is performed to maintain cache consistency, then data consistency is improved, but the number of memory transactions increases reducing performance
Solution Approach 1:
The patent performs preliminary rinsing of dirty cache lines before they can cause consistency issues or require write-through operations. By proactively clearing the cache during idle periods, it prevents future consistency conflicts and eliminates the need for additional write-through transactions, thus maintaining data consistency without sacrificing throughput.
Data Source
AI summary
A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.