Cache Memory RMW Pipeline for Partial Writes and ECC Merging
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Solution Overview
Problem
Existing memory systems in SoCs face inefficiencies in managing read-modify-write operations, particularly with partial writes, leading to increased processing time and power consumption due to the need for additional read and write transactions.
Innovation Solution
Implementing a Read-Modify-Write (RMW) pipeline with a holding buffer, anchor stage, merge stage, and syndrome generation stage to manage partial writes by reading conforming data, merging it with the write payload, and generating an ECC syndrome before writing to cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory write operations are used for partial writes, then additional read and write transactions are required, but processing time and power consumption increase
Solution Approach 1:
The patent implements a holding buffer that pre-stores the payload data before the write operation is complete. By preparing the data in advance and maintaining it in the holding buffer during the read-merge-write process, the system avoids re-reading or re-transmitting the payload, thereby reducing processing time while maintaining correctness for partial write operations
Solution Approach 2:
The patent segments the memory write operation into distinct stages: holding the payload, reading conforming data, merging data, generating ECC syndrome, and writing to cache. This segmentation allows each stage to be optimized independently and enables parallel processing where possible, improving overall processing speed while handling partial writes efficiently
2Productivity
If traditional memory write operations are used for partial writes, then additional read and write transactions are required, but power consumption increases
Solution Approach 1:
By pre-storing the payload in the holding buffer before the write transaction begins, the system eliminates the need to re-transmit or re-read the payload during the operation. This preliminary action reduces the number of active transactions on the memory bus, thereby reducing dynamic power consumption while maintaining processing efficiency for partial writes
Solution Approach 2:
The patent extracts the payload holding function into a separate holding buffer component, isolating it from the main write path. This extraction allows the payload to be staged independently without requiring continuous bus transactions, reducing power consumption while maintaining the ability to handle partial write operations efficiently
3Reliability
If partial writes are handled traditionally, then multiple transactions are needed, but device complexity increases
Solution Approach 1:
The patent segments the RMW operation into distinct pipeline stages (holding, reading, merging, ECC generation, writing), with each stage having a specific responsibility. This segmentation improves reliability by ensuring each operation is performed correctly in sequence, while the modular structure manages complexity through clear stage boundaries and defined interfaces
Solution Approach 2:
The holding buffer acts as an intermediary component that decouples the payload storage from the complex RMW operations. This intermediary simplifies the overall system architecture by providing a stable, pre-prepared data source that doesn't require re-access during the multi-stage RMW process, thereby reducing the complexity burden while maintaining data integrity
Data Source
AI summary
In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.