Hardware Cache Scrambling for VM Side-Channel Mitigation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Virtualization systems face side-channel attacks due to shared cache resources, where an attacker VM can exploit the cache access patterns of a victim VM to extract confidential information, such as encryption keys, leading to potential information leakage and compromised isolation between VMs.

Innovation Solution

Implementing hardware-assisted obscuring of cache access patterns through a scrambler that uses Cache Scrambling Keys (CSKs) to randomly map cache lines, making cache access patterns unpredictable and preventing attackers from inferring victim VM activities by modifying cache access indices and tags, thereby obscuring cache access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a shared last level cache (LLC) is used among multiple guest VMs, then resource utilization and efficiency are improved, but information leakage and security isolation between VMs deteriorate due to side-channel attacks

Engineering Contradiction:
Improveresource utilizationVSAvoidinformation leakage
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic cache set mapping where the mapping between cache sets and physical address tags changes over time through epoch transitions. During each epoch, a specific scrambling key is used to dynamically remap cache sets, making the cache access pattern unpredictable to attackers while maintaining efficient cache operation. This dynamic remapping prevents side-channel attacks by ensuring that an attacker VM cannot reliably infer victim VM's cache access patterns across epoch boundaries.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the mapping parameter (cache set to tag association) by applying scrambling keys that transform the relationship between cache sets and physical addresses. Each epoch uses a different scrambling key, effectively changing the parameter mapping to obscure the true access patterns. This parameter transformation allows the shared cache to maintain high utilization while preventing information leakage through altered address mapping relationships.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If cache access patterns are made unpredictable through scrambling, then security and isolation between VMs are improved, but cache performance and access efficiency may deteriorate

Engineering Contradiction:
Improveisolation between VMsVSAvoidcache access efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary cache flushing and remapping actions at epoch boundaries before new cache operations begin. By proactively invalidating cache sets during epoch transitions and establishing new scrambled mappings in advance, the system ensures security isolation is maintained without causing performance degradation during normal cache operations within each epoch. The preliminary action confines the overhead to transition periods rather than continuous operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic epoch transitions that occur at predetermined intervals, during which cache scrambling keys are updated and cache sets are flushed. This periodic action creates a rhythm of security reinforcement that maintains isolation between VMs while allowing efficient cache operation during each epoch period. The periodic nature ensures that security measures are applied systematically without continuously disrupting cache performance.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11620238B1Hardware blinding of memory access with epoch transitions
Publication Date: 2023.04.04 AMAZON TECH INC
  • US11620238B1 patent drawing
  • US11620238B1 patent drawing
  • US11620238B1 patent drawing

AI summary

A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a main memory, a shared cache and a cache controller for the shared cache including a scrambling function that scrambles addresses of memory accesses according to the respective scrambling keys selected for a sequence of time periods. Different cache tiers may implement different scrambling functions optimized to the architecture of each cache tier. Scrambling keys may be updated to reduce predictability of shared cache to memory address mappings. These updates may occur opportunistically, on demand or on specified schedule. Multiple scrambling keys may be simultaneously active during transitions between active time periods.