Cache Memory Scrubbing via Tag Array Status Monitoring
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Solution Overview
Problem
Cache memories face increased soft error rates (SER) due to technological scaling and power supply issues, particularly during low power states which contribute to error accumulation beyond error correction capabilities.
Innovation Solution
Implementing a differential scrubbing rate for cache memory arrays, where the tag array is scrubbed at a smaller interval than the data array, with modified entries scrubbed more frequently and clean entries scrubbed at a lower rate to maintain data integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the cache memory is retained in a low power state during inactive periods, then power consumption is reduced, but soft error rates increase due to error accumulation
Solution Approach 1:
The patent implements periodic scrubbing operations during low power states to detect and correct soft errors before they accumulate beyond correction capabilities. The scrubbing controller activates error correction codes periodically to maintain data integrity while the cache remains in low power mode, thus resolving the contradiction between power savings and error accumulation.
2Speed
If technology scaling is continued to improve performance, then processing speed increases, but bit cell sensitivity to soft errors increases
Solution Approach 1:
The patent applies error correction codes in advance during scrubbing operations to prevent soft errors from affecting data integrity. By proactively detecting and correcting errors before they impact processor operations, the system enables continued technology scaling without compromising reliability despite increased bit cell sensitivity.
3Device complexity
If uniform scrubbing rate is applied to both tag array and data array, then implementation is simplified, but power consumption increases due to unnecessary scrubbing of clean entries
Solution Approach 1:
The patent implements differential scrubbing rates where modified cache entries are scrubbed more frequently than clean entries. The scrubbing controller examines the modified bit status and applies appropriate scrubbing intervals: faster scrubbing for modified entries that require frequent error checking, and slower scrubbing for clean entries. This local differentiation reduces overall power consumption while maintaining error resilience where needed.
4Reliability
If faster scrubbing rate is applied to maintain error resilience, then error detection capability improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic scrubbing rates that adjust based on cache entry status. Modified entries with the modified bit set trigger faster scrubbing intervals for enhanced error detection, while clean entries use slower scrubbing intervals to reduce power consumption. This dynamic adaptation allows the system to optimize the balance between error resilience and power usage based on actual cache content and state.
Data Source
AI summary
A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.